Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 The Chromium OS Authors. All rights reserved. |
| 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | * |
| 6 | * This is a driver for a SPI interfaced TPM2 device. |
| 7 | * |
| 8 | * It assumes that the required SPI interface has been initialized before the |
| 9 | * driver is started. A 'sruct spi_slave' pointer passed at initialization is |
| 10 | * used to direct traffic to the correct SPI interface. This dirver does not |
| 11 | * provide a way to instantiate multiple TPM devices. Also, to keep things |
| 12 | * simple, the driver unconditionally uses of TPM locality zero. |
| 13 | * |
| 14 | * References to documentation are based on the TCG issued "TPM Profile (PTP) |
| 15 | * Specification Revision 00.43". |
| 16 | */ |
| 17 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 18 | #include <arch/early_variables.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 19 | #include <commonlib/endian.h> |
| 20 | #include <console/console.h> |
| 21 | #include <delay.h> |
| 22 | #include <endian.h> |
| 23 | #include <string.h> |
| 24 | #include <timer.h> |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 25 | #include <tpm.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 26 | |
| 27 | #include "tpm.h" |
| 28 | |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 29 | #define TPM_LOCALITY_0_SPI_BASE 0x00d40000 |
| 30 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 31 | /* Assorted TPM2 registers for interface type FIFO. */ |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 32 | #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) |
| 33 | #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) |
| 34 | #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) |
| 35 | #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) |
| 36 | #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 37 | #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 38 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 39 | /* SPI slave structure for TPM device. */ |
| 40 | static struct spi_slave g_spi_slave CAR_GLOBAL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 41 | |
| 42 | /* Cached TPM device identification. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 43 | static struct tpm2_info g_tpm_info CAR_GLOBAL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of |
| 47 | * debug traces. Right now it is either 0 or 1. |
| 48 | */ |
| 49 | static const int debug_level_ = CONFIG_DEBUG_TPM; |
| 50 | |
| 51 | /* Locality management bits (in TPM_ACCESS_REG) */ |
| 52 | enum tpm_access_bits { |
| 53 | tpm_reg_valid_sts = (1 << 7), |
| 54 | active_locality = (1 << 5), |
| 55 | request_use = (1 << 1), |
| 56 | tpm_establishment = (1 << 0), |
| 57 | }; |
| 58 | |
| 59 | /* |
| 60 | * Variuous fields of the TPM status register, arguably the most important |
| 61 | * register when interfacing to a TPM. |
| 62 | */ |
| 63 | enum tpm_sts_bits { |
| 64 | tpm_family_shift = 26, |
| 65 | tpm_family_mask = ((1 << 2) - 1), /* 2 bits wide. */ |
| 66 | tpm_family_tpm2 = 1, |
| 67 | reset_establishment_bit = (1 << 25), |
| 68 | command_cancel = (1 << 24), |
| 69 | burst_count_shift = 8, |
| 70 | burst_count_mask = ((1 << 16) - 1), /* 16 bits wide. */ |
| 71 | sts_valid = (1 << 7), |
| 72 | command_ready = (1 << 6), |
| 73 | tpm_go = (1 << 5), |
| 74 | data_avail = (1 << 4), |
| 75 | expect = (1 << 3), |
| 76 | self_test_done = (1 << 2), |
| 77 | response_retry = (1 << 1), |
| 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * SPI frame header for TPM transactions is 4 bytes in size, it is described |
| 82 | * in section "6.4.6 Spi Bit Protocol". |
| 83 | */ |
| 84 | typedef struct { |
| 85 | unsigned char body[4]; |
| 86 | } spi_frame_header; |
| 87 | |
| 88 | void tpm2_get_info(struct tpm2_info *info) |
| 89 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 90 | *info = car_get_var(g_tpm_info); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 91 | } |
| 92 | |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 93 | __attribute__((weak)) int tis_plat_irq_status(void) |
| 94 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 95 | static int warning_displayed CAR_GLOBAL; |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 96 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 97 | if (!car_get_var(warning_displayed)) { |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 98 | printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 10ms to wait on Cr50!\n"); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 99 | car_set_var(warning_displayed, 1); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 100 | } |
| 101 | mdelay(10); |
| 102 | |
| 103 | return 1; |
| 104 | } |
| 105 | |
| 106 | /* |
| 107 | * TPM may trigger a irq after finish processing previous transfer. |
| 108 | * Waiting for this irq to sync tpm status. |
| 109 | * |
| 110 | * Returns 1 on success, 0 on failure (timeout). |
| 111 | */ |
| 112 | static int tpm_sync(void) |
| 113 | { |
| 114 | struct stopwatch sw; |
| 115 | |
| 116 | stopwatch_init_usecs_expire(&sw, 10 * 1000); |
| 117 | while (!tis_plat_irq_status()) { |
| 118 | if (stopwatch_expired(&sw)) { |
| 119 | printk(BIOS_ERR, "Timeout wait for tpm irq!\n"); |
| 120 | return 0; |
| 121 | } |
| 122 | } |
| 123 | return 1; |
| 124 | } |
| 125 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 126 | /* |
| 127 | * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte |
| 128 | * header is sent to the TPM, the master waits til TPM is ready to continue. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 129 | * |
| 130 | * Returns 1 on success, 0 on failure (TPM SPI flow control timeout.) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 131 | */ |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 132 | static int start_transaction(int read_write, size_t bytes, unsigned addr) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 133 | { |
| 134 | spi_frame_header header; |
| 135 | uint8_t byte; |
| 136 | int i; |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 137 | struct stopwatch sw; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 138 | static int tpm_sync_needed CAR_GLOBAL; |
| 139 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 140 | |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 141 | /* Wait for tpm to finish previous transaction if needed */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 142 | if (car_get_var(tpm_sync_needed)) |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 143 | tpm_sync(); |
| 144 | else |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 145 | car_set_var(tpm_sync_needed, 1); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 146 | |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 147 | /* Try to wake cr50 if it is asleep. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 148 | spi_claim_bus(spi_slave); |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 149 | udelay(1); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 150 | spi_release_bus(spi_slave); |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 151 | udelay(100); |
| 152 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 153 | /* |
| 154 | * The first byte of the frame header encodes the transaction type |
| 155 | * (read or write) and transfer size (set to lentgh - 1), limited to |
| 156 | * 64 bytes. |
| 157 | */ |
| 158 | header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); |
| 159 | |
| 160 | /* The rest of the frame header is the TPM register address. */ |
| 161 | for (i = 0; i < 3; i++) |
| 162 | header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; |
| 163 | |
| 164 | /* CS assert wakes up the slave. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 165 | spi_claim_bus(spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * The TCG TPM over SPI specification introduces the notion of SPI |
| 169 | * flow control (Section "6.4.5 Flow Control"). |
| 170 | * |
| 171 | * Again, the slave (TPM device) expects each transaction to start |
| 172 | * with a 4 byte header trasmitted by master. The header indicates if |
| 173 | * the master needs to read or write a register, and the register |
| 174 | * address. |
| 175 | * |
| 176 | * If the slave needs to stall the transaction (for instance it is not |
| 177 | * ready to send the register value to the master), it sets the MOSI |
| 178 | * line to 0 during the last clock of the 4 byte header. In this case |
| 179 | * the master is supposed to start polling the SPI bus, one byte at |
| 180 | * time, until the last bit in the received byte (transferred during |
| 181 | * the last clock of the byte) is set to 1. |
| 182 | * |
| 183 | * Due to some SPI controllers' shortcomings (Rockchip comes to |
| 184 | * mind...) we trasmit the 4 byte header without checking the byte |
| 185 | * transmitted by the TPM during the transaction's last byte. |
| 186 | * |
| 187 | * We know that cr50 is guaranteed to set the flow control bit to 0 |
| 188 | * during the header transfer, but real TPM2 might be fast enough not |
| 189 | * to require to stall the master, this would present an issue. |
| 190 | * crosbug.com/p/52132 has been opened to track this. |
| 191 | */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 192 | spi_xfer(spi_slave, header.body, sizeof(header.body), NULL, 0); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 193 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 194 | /* |
| 195 | * Now poll the bus until TPM removes the stall bit. Give it up to 100 |
| 196 | * ms to sort it out - it could be saving stuff in nvram at some |
| 197 | * point. |
| 198 | */ |
| 199 | stopwatch_init_msecs_expire(&sw, 100); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 200 | do { |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 201 | if (stopwatch_expired(&sw)) { |
| 202 | printk(BIOS_ERR, "TPM flow control failure\n"); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 203 | spi_release_bus(spi_slave); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 204 | return 0; |
| 205 | } |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 206 | spi_xfer(spi_slave, NULL, 0, &byte, 1); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 207 | } while (!(byte & 1)); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 208 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | /* |
| 212 | * Print out the contents of a buffer, if debug is enabled. Skip registers |
| 213 | * other than FIFO, unless debug_level_ is 2. |
| 214 | */ |
| 215 | static void trace_dump(const char *prefix, uint32_t reg, |
| 216 | size_t bytes, const uint8_t *buffer, |
| 217 | int force) |
| 218 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 219 | static char prev_prefix CAR_GLOBAL; |
| 220 | static unsigned prev_reg CAR_GLOBAL; |
| 221 | static int current_char CAR_GLOBAL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 222 | const int BYTES_PER_LINE = 32; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 223 | int *current_char_ptr = car_get_var_ptr(¤t_char); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 224 | |
| 225 | if (!force) { |
| 226 | if (!debug_level_) |
| 227 | return; |
| 228 | |
| 229 | if ((debug_level_ < 2) && (reg != TPM_DATA_FIFO_REG)) |
| 230 | return; |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Do not print register address again if the last dump print was for |
| 235 | * that register. |
| 236 | */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 237 | if ((car_get_var(prev_prefix) != *prefix) || |
| 238 | (car_get_var(prev_reg) != reg)) { |
| 239 | car_set_var(prev_prefix, *prefix); |
| 240 | car_set_var(prev_reg, reg); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 241 | printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 242 | *current_char_ptr = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { |
| 246 | /* |
| 247 | * This must be a regular register address, print the 32 bit |
| 248 | * value. |
| 249 | */ |
| 250 | printk(BIOS_DEBUG, " %8.8x", *(const uint32_t *)buffer); |
| 251 | } else { |
| 252 | int i; |
| 253 | |
| 254 | /* |
| 255 | * Data read from or written to FIFO or not in 4 byte |
| 256 | * quantiites is printed byte at a time. |
| 257 | */ |
| 258 | for (i = 0; i < bytes; i++) { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 259 | if (*current_char_ptr && |
| 260 | !(*current_char_ptr % BYTES_PER_LINE)) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 261 | printk(BIOS_DEBUG, "\n "); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 262 | *current_char_ptr = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 263 | } |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 264 | (*current_char_ptr)++; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 265 | printk(BIOS_DEBUG, " %2.2x", buffer[i]); |
| 266 | } |
| 267 | } |
| 268 | } |
| 269 | |
| 270 | /* |
| 271 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 272 | * write the actual bytes to the register. |
| 273 | */ |
| 274 | static void write_bytes(const void *buffer, size_t bytes) |
| 275 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 276 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
| 277 | spi_xfer(spi_slave, buffer, bytes, NULL, 0); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | /* |
| 281 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 282 | * read the actual bytes from the register. |
| 283 | */ |
| 284 | static void read_bytes(void *buffer, size_t bytes) |
| 285 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 286 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
| 287 | spi_xfer(spi_slave, NULL, 0, buffer, bytes); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | /* |
| 291 | * To write a register, start transaction, transfer data to the TPM, deassert |
| 292 | * CS when done. |
| 293 | * |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 294 | * Returns one to indicate success, zero to indicate failure. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 295 | */ |
| 296 | static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) |
| 297 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 298 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 299 | trace_dump("W", reg_number, bytes, buffer, 0); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 300 | if (!start_transaction(false, bytes, reg_number)) |
| 301 | return 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 302 | write_bytes(buffer, bytes); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 303 | spi_release_bus(spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 304 | return 1; |
| 305 | } |
| 306 | |
| 307 | /* |
| 308 | * To read a register, start transaction, transfer data from the TPM, deassert |
| 309 | * CS when done. |
| 310 | * |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 311 | * Returns one to indicate success, zero to indicate failure. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 312 | */ |
| 313 | static int tpm2_read_reg(unsigned reg_number, void *buffer, size_t bytes) |
| 314 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 315 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 316 | if (!start_transaction(true, bytes, reg_number)) { |
| 317 | memset(buffer, 0, bytes); |
| 318 | return 0; |
| 319 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 320 | read_bytes(buffer, bytes); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 321 | spi_release_bus(spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 322 | trace_dump("R", reg_number, bytes, buffer, 0); |
| 323 | return 1; |
| 324 | } |
| 325 | |
| 326 | /* |
| 327 | * Status register is accessed often, wrap reading and writing it into |
| 328 | * dedicated functions. |
| 329 | */ |
| 330 | static int read_tpm_sts(uint32_t *status) |
| 331 | { |
| 332 | return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); |
| 333 | } |
| 334 | |
| 335 | static int write_tpm_sts(uint32_t status) |
| 336 | { |
| 337 | return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); |
| 338 | } |
| 339 | |
| 340 | /* |
| 341 | * The TPM may limit the transaction bytes count (burst count) below the 64 |
| 342 | * bytes max. The current value is available as a field of the status |
| 343 | * register. |
| 344 | */ |
| 345 | static uint32_t get_burst_count(void) |
| 346 | { |
| 347 | uint32_t status; |
| 348 | |
| 349 | read_tpm_sts(&status); |
| 350 | return (status >> burst_count_shift) & burst_count_mask; |
| 351 | } |
| 352 | |
| 353 | int tpm2_init(struct spi_slave *spi_if) |
| 354 | { |
| 355 | uint32_t did_vid, status; |
| 356 | uint8_t cmd; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 357 | struct tpm2_info *tpm_info = car_get_var_ptr(&g_tpm_info); |
| 358 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 359 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 360 | memcpy(spi_slave, spi_if, sizeof(*spi_if)); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 361 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 362 | /* |
| 363 | * It is enough to check the first register read error status to bail |
| 364 | * out in case of malfunctioning TPM. |
| 365 | */ |
| 366 | if (!tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid))) |
| 367 | return -1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 368 | |
| 369 | /* Try claiming locality zero. */ |
| 370 | tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 371 | if ((cmd & (active_locality & tpm_reg_valid_sts)) == |
| 372 | (active_locality & tpm_reg_valid_sts)) { |
| 373 | /* |
| 374 | * Locality active - maybe reset line is not connected? |
| 375 | * Release the locality and try again |
| 376 | */ |
| 377 | cmd = active_locality; |
| 378 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 379 | tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 380 | } |
| 381 | |
| 382 | /* The tpm_establishment bit can be either set or not, ignore it. */ |
| 383 | if ((cmd & ~tpm_establishment) != tpm_reg_valid_sts) { |
| 384 | printk(BIOS_ERR, "invalid reset status: %#x\n", cmd); |
| 385 | return -1; |
| 386 | } |
| 387 | |
| 388 | cmd = request_use; |
| 389 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 390 | tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 391 | if ((cmd & ~tpm_establishment) != |
| 392 | (tpm_reg_valid_sts | active_locality)) { |
| 393 | printk(BIOS_ERR, "failed to claim locality 0, status: %#x\n", |
| 394 | cmd); |
| 395 | return -1; |
| 396 | } |
| 397 | |
| 398 | read_tpm_sts(&status); |
| 399 | if (((status >> tpm_family_shift) & tpm_family_mask) != |
| 400 | tpm_family_tpm2) { |
| 401 | printk(BIOS_ERR, "unexpected TPM family value, status: %#x\n", |
| 402 | status); |
| 403 | return -1; |
| 404 | } |
| 405 | |
| 406 | /* |
| 407 | * Locality claimed, read the revision value and set up the tpm_info |
| 408 | * structure. |
| 409 | */ |
| 410 | tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 411 | tpm_info->vendor_id = did_vid & 0xffff; |
| 412 | tpm_info->device_id = did_vid >> 16; |
| 413 | tpm_info->revision = cmd; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 414 | |
| 415 | printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 416 | tpm_info->vendor_id, tpm_info->device_id, tpm_info->revision); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 417 | |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 418 | /* Let's report device FW version if available. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 419 | if (tpm_info->vendor_id == 0x1ae0) { |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 420 | int chunk_count = 0; |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 421 | size_t chunk_size; |
| 422 | /* |
| 423 | * let's read 50 bytes at a time; leave room for the trailing |
| 424 | * zero. |
| 425 | */ |
| 426 | char vstr[51]; |
| 427 | |
| 428 | chunk_size = sizeof(vstr) - 1; |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 429 | |
| 430 | printk(BIOS_INFO, "Firmware version: "); |
| 431 | |
| 432 | /* |
| 433 | * Does not really matter what's written, this just makes sure |
| 434 | * the version is reported from the beginning. |
| 435 | */ |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 436 | tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 437 | |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 438 | /* Print it out in sizeof(vstr) - 1 byte chunks. */ |
| 439 | vstr[chunk_size] = 0; |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 440 | do { |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 441 | tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 442 | printk(BIOS_INFO, "%s", vstr); |
| 443 | |
| 444 | /* |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 445 | * While string is not over, and is no longer than 300 |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 446 | * characters. |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 447 | */ |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 448 | } while (vstr[chunk_size - 1] && |
| 449 | (chunk_count++ < (300 / chunk_size))); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 450 | |
| 451 | printk(BIOS_INFO, "\n"); |
| 452 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 453 | return 0; |
| 454 | } |
| 455 | |
| 456 | /* |
| 457 | * This is in seconds, certain TPM commands, like key generation, can take |
| 458 | * long time to complete. |
| 459 | * |
| 460 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 461 | * failure. |
| 462 | */ |
| 463 | #define MAX_STATUS_TIMEOUT 120 |
| 464 | static int wait_for_status(uint32_t status_mask, uint32_t status_expected) |
| 465 | { |
| 466 | uint32_t status; |
| 467 | struct stopwatch sw; |
| 468 | |
| 469 | stopwatch_init_usecs_expire(&sw, MAX_STATUS_TIMEOUT * 1000 * 1000); |
| 470 | do { |
| 471 | udelay(1000); |
| 472 | if (stopwatch_expired(&sw)) { |
| 473 | printk(BIOS_ERR, "failed to get expected status %x\n", |
| 474 | status_expected); |
| 475 | return false; |
| 476 | } |
| 477 | read_tpm_sts(&status); |
| 478 | } while ((status & status_mask) != status_expected); |
| 479 | |
| 480 | return 1; |
| 481 | } |
| 482 | |
| 483 | enum fifo_transfer_direction { |
| 484 | fifo_transmit = 0, |
| 485 | fifo_receive = 1 |
| 486 | }; |
| 487 | |
| 488 | /* Union allows to avoid casting away 'const' on transmit buffers. */ |
| 489 | union fifo_transfer_buffer { |
| 490 | uint8_t *rx_buffer; |
| 491 | const uint8_t *tx_buffer; |
| 492 | }; |
| 493 | |
| 494 | /* |
| 495 | * Transfer requested number of bytes to or from TPM FIFO, accounting for the |
| 496 | * current burst count value. |
| 497 | */ |
| 498 | static void fifo_transfer(size_t transfer_size, |
| 499 | union fifo_transfer_buffer buffer, |
| 500 | enum fifo_transfer_direction direction) |
| 501 | { |
| 502 | size_t transaction_size; |
| 503 | size_t burst_count; |
| 504 | size_t handled_so_far = 0; |
| 505 | |
| 506 | do { |
| 507 | do { |
| 508 | /* Could be zero when TPM is busy. */ |
| 509 | burst_count = get_burst_count(); |
| 510 | } while (!burst_count); |
| 511 | |
| 512 | transaction_size = transfer_size - handled_so_far; |
| 513 | transaction_size = MIN(transaction_size, burst_count); |
| 514 | |
| 515 | /* |
| 516 | * The SPI frame header does not allow to pass more than 64 |
| 517 | * bytes. |
| 518 | */ |
| 519 | transaction_size = MIN(transaction_size, 64); |
| 520 | |
| 521 | if (direction == fifo_receive) |
| 522 | tpm2_read_reg(TPM_DATA_FIFO_REG, |
| 523 | buffer.rx_buffer + handled_so_far, |
| 524 | transaction_size); |
| 525 | else |
| 526 | tpm2_write_reg(TPM_DATA_FIFO_REG, |
| 527 | buffer.tx_buffer + handled_so_far, |
| 528 | transaction_size); |
| 529 | |
| 530 | handled_so_far += transaction_size; |
| 531 | |
| 532 | } while (handled_so_far != transfer_size); |
| 533 | } |
| 534 | |
| 535 | size_t tpm2_process_command(const void *tpm2_command, size_t command_size, |
| 536 | void *tpm2_response, size_t max_response) |
| 537 | { |
| 538 | uint32_t status; |
| 539 | uint32_t expected_status_bits; |
| 540 | size_t payload_size; |
| 541 | size_t bytes_to_go; |
| 542 | const uint8_t *cmd_body = tpm2_command; |
| 543 | uint8_t *rsp_body = tpm2_response; |
| 544 | union fifo_transfer_buffer fifo_buffer; |
| 545 | const int HEADER_SIZE = 6; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 546 | struct tpm2_info *tpm_info = car_get_var_ptr(&g_tpm_info); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 547 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 548 | /* Do not try using an uninitialized TPM. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame^] | 549 | if (!tpm_info->vendor_id) |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 550 | return 0; |
| 551 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 552 | /* Skip the two byte tag, read the size field. */ |
| 553 | payload_size = read_be32(cmd_body + 2); |
| 554 | |
| 555 | /* Sanity check. */ |
| 556 | if (payload_size != command_size) { |
| 557 | printk(BIOS_ERR, |
| 558 | "Command size mismatch: encoded %zd != requested %zd\n", |
| 559 | payload_size, command_size); |
| 560 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 561 | printk(BIOS_DEBUG, "\n"); |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | /* Let the TPM know that the command is coming. */ |
| 566 | write_tpm_sts(command_ready); |
| 567 | |
| 568 | /* |
| 569 | * Tpm commands and responses written to and read from the FIFO |
| 570 | * register (0x24) are datagrams of variable size, prepended by a 6 |
| 571 | * byte header. |
| 572 | * |
| 573 | * The specification description of the state machine is a bit vague, |
| 574 | * but from experience it looks like there is no need to wait for the |
| 575 | * sts.expect bit to be set, at least with the 9670 and cr50 devices. |
| 576 | * Just write the command into FIFO, making sure not to exceed the |
| 577 | * burst count or the maximum PDU size, whatever is smaller. |
| 578 | */ |
| 579 | fifo_buffer.tx_buffer = cmd_body; |
| 580 | fifo_transfer(command_size, fifo_buffer, fifo_transmit); |
| 581 | |
| 582 | /* Now tell the TPM it can start processing the command. */ |
| 583 | write_tpm_sts(tpm_go); |
| 584 | |
| 585 | /* Now wait for it to report that the response is ready. */ |
| 586 | expected_status_bits = sts_valid | data_avail; |
| 587 | if (!wait_for_status(expected_status_bits, expected_status_bits)) { |
| 588 | /* |
| 589 | * If timed out, which should never happen, let's at least |
| 590 | * print out the offending command. |
| 591 | */ |
| 592 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 593 | printk(BIOS_DEBUG, "\n"); |
| 594 | return 0; |
| 595 | } |
| 596 | |
| 597 | /* |
| 598 | * The response is ready, let's read it. First we read the FIFO |
| 599 | * payload header, to see how much data to expect. The response header |
| 600 | * size is fixed to six bytes, the total payload size is stored in |
| 601 | * network order in the last four bytes. |
| 602 | */ |
| 603 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body, HEADER_SIZE); |
| 604 | |
| 605 | /* Find out the total payload size, skipping the two byte tag. */ |
| 606 | payload_size = read_be32(rsp_body + 2); |
| 607 | |
| 608 | if (payload_size > max_response) { |
| 609 | /* |
| 610 | * TODO(vbendeb): at least drain the FIFO here or somehow let |
| 611 | * the TPM know that the response can be dropped. |
| 612 | */ |
| 613 | printk(BIOS_ERR, " tpm response too long (%zd bytes)", |
| 614 | payload_size); |
| 615 | return 0; |
| 616 | } |
| 617 | |
| 618 | /* |
| 619 | * Now let's read all but the last byte in the FIFO to make sure the |
| 620 | * status register is showing correct flow control bits: 'more data' |
| 621 | * until the last byte and then 'no more data' once the last byte is |
| 622 | * read. |
| 623 | */ |
| 624 | bytes_to_go = payload_size - 1 - HEADER_SIZE; |
| 625 | fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; |
| 626 | fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); |
| 627 | |
| 628 | /* Verify that there is still data to read. */ |
| 629 | read_tpm_sts(&status); |
| 630 | if ((status & expected_status_bits) != expected_status_bits) { |
| 631 | printk(BIOS_ERR, "unexpected intermediate status %#x\n", |
| 632 | status); |
| 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | /* Read the last byte of the PDU. */ |
| 637 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body + payload_size - 1, 1); |
| 638 | |
| 639 | /* Terminate the dump, if enabled. */ |
| 640 | if (debug_level_) |
| 641 | printk(BIOS_DEBUG, "\n"); |
| 642 | |
| 643 | /* Verify that 'data available' is not asseretd any more. */ |
| 644 | read_tpm_sts(&status); |
| 645 | if ((status & expected_status_bits) != sts_valid) { |
| 646 | printk(BIOS_ERR, "unexpected final status %#x\n", status); |
| 647 | return 0; |
| 648 | } |
| 649 | |
| 650 | /* Move the TPM back to idle state. */ |
| 651 | write_tpm_sts(command_ready); |
| 652 | |
| 653 | return payload_size; |
| 654 | } |