Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 The Chromium OS Authors. All rights reserved. |
| 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | * |
| 6 | * This is a driver for a SPI interfaced TPM2 device. |
| 7 | * |
| 8 | * It assumes that the required SPI interface has been initialized before the |
| 9 | * driver is started. A 'sruct spi_slave' pointer passed at initialization is |
| 10 | * used to direct traffic to the correct SPI interface. This dirver does not |
| 11 | * provide a way to instantiate multiple TPM devices. Also, to keep things |
| 12 | * simple, the driver unconditionally uses of TPM locality zero. |
| 13 | * |
| 14 | * References to documentation are based on the TCG issued "TPM Profile (PTP) |
| 15 | * Specification Revision 00.43". |
| 16 | */ |
| 17 | |
| 18 | #include <commonlib/endian.h> |
| 19 | #include <console/console.h> |
| 20 | #include <delay.h> |
| 21 | #include <endian.h> |
| 22 | #include <string.h> |
| 23 | #include <timer.h> |
| 24 | |
| 25 | #include "tpm.h" |
| 26 | |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame^] | 27 | #define TPM_LOCALITY_0_SPI_BASE 0x00d40000 |
| 28 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 29 | /* Assorted TPM2 registers for interface type FIFO. */ |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame^] | 30 | #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) |
| 31 | #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) |
| 32 | #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) |
| 33 | #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) |
| 34 | #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 35 | |
| 36 | /* SPI Interface descriptor used by the driver. */ |
| 37 | struct tpm_spi_if { |
| 38 | struct spi_slave *slave; |
| 39 | int (*cs_assert)(struct spi_slave *slave); |
| 40 | void (*cs_deassert)(struct spi_slave *slave); |
| 41 | int (*xfer)(struct spi_slave *slave, const void *dout, |
| 42 | unsigned bytesout, void *din, |
| 43 | unsigned bytesin); |
| 44 | }; |
| 45 | |
| 46 | /* Use the common SPI driver wrapper as the interface callbacks. */ |
| 47 | static struct tpm_spi_if tpm_if = { |
| 48 | .cs_assert = spi_claim_bus, |
| 49 | .cs_deassert = spi_release_bus, |
| 50 | .xfer = spi_xfer |
| 51 | }; |
| 52 | |
| 53 | /* Cached TPM device identification. */ |
| 54 | struct tpm2_info tpm_info; |
| 55 | |
| 56 | /* |
| 57 | * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of |
| 58 | * debug traces. Right now it is either 0 or 1. |
| 59 | */ |
| 60 | static const int debug_level_ = CONFIG_DEBUG_TPM; |
| 61 | |
| 62 | /* Locality management bits (in TPM_ACCESS_REG) */ |
| 63 | enum tpm_access_bits { |
| 64 | tpm_reg_valid_sts = (1 << 7), |
| 65 | active_locality = (1 << 5), |
| 66 | request_use = (1 << 1), |
| 67 | tpm_establishment = (1 << 0), |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * Variuous fields of the TPM status register, arguably the most important |
| 72 | * register when interfacing to a TPM. |
| 73 | */ |
| 74 | enum tpm_sts_bits { |
| 75 | tpm_family_shift = 26, |
| 76 | tpm_family_mask = ((1 << 2) - 1), /* 2 bits wide. */ |
| 77 | tpm_family_tpm2 = 1, |
| 78 | reset_establishment_bit = (1 << 25), |
| 79 | command_cancel = (1 << 24), |
| 80 | burst_count_shift = 8, |
| 81 | burst_count_mask = ((1 << 16) - 1), /* 16 bits wide. */ |
| 82 | sts_valid = (1 << 7), |
| 83 | command_ready = (1 << 6), |
| 84 | tpm_go = (1 << 5), |
| 85 | data_avail = (1 << 4), |
| 86 | expect = (1 << 3), |
| 87 | self_test_done = (1 << 2), |
| 88 | response_retry = (1 << 1), |
| 89 | }; |
| 90 | |
| 91 | /* |
| 92 | * SPI frame header for TPM transactions is 4 bytes in size, it is described |
| 93 | * in section "6.4.6 Spi Bit Protocol". |
| 94 | */ |
| 95 | typedef struct { |
| 96 | unsigned char body[4]; |
| 97 | } spi_frame_header; |
| 98 | |
| 99 | void tpm2_get_info(struct tpm2_info *info) |
| 100 | { |
| 101 | *info = tpm_info; |
| 102 | } |
| 103 | |
| 104 | /* |
| 105 | * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte |
| 106 | * header is sent to the TPM, the master waits til TPM is ready to continue. |
| 107 | */ |
| 108 | static void start_transaction(int read_write, size_t bytes, unsigned addr) |
| 109 | { |
| 110 | spi_frame_header header; |
| 111 | uint8_t byte; |
| 112 | int i; |
| 113 | |
| 114 | /* |
| 115 | * Give it 10 ms. TODO(vbendeb): remove this once cr50 SPS TPM driver |
| 116 | * performance is fixed. |
| 117 | */ |
| 118 | mdelay(10); |
| 119 | |
| 120 | /* |
| 121 | * The first byte of the frame header encodes the transaction type |
| 122 | * (read or write) and transfer size (set to lentgh - 1), limited to |
| 123 | * 64 bytes. |
| 124 | */ |
| 125 | header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); |
| 126 | |
| 127 | /* The rest of the frame header is the TPM register address. */ |
| 128 | for (i = 0; i < 3; i++) |
| 129 | header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; |
| 130 | |
| 131 | /* CS assert wakes up the slave. */ |
| 132 | tpm_if.cs_assert(tpm_if.slave); |
| 133 | |
| 134 | /* |
| 135 | * The TCG TPM over SPI specification introduces the notion of SPI |
| 136 | * flow control (Section "6.4.5 Flow Control"). |
| 137 | * |
| 138 | * Again, the slave (TPM device) expects each transaction to start |
| 139 | * with a 4 byte header trasmitted by master. The header indicates if |
| 140 | * the master needs to read or write a register, and the register |
| 141 | * address. |
| 142 | * |
| 143 | * If the slave needs to stall the transaction (for instance it is not |
| 144 | * ready to send the register value to the master), it sets the MOSI |
| 145 | * line to 0 during the last clock of the 4 byte header. In this case |
| 146 | * the master is supposed to start polling the SPI bus, one byte at |
| 147 | * time, until the last bit in the received byte (transferred during |
| 148 | * the last clock of the byte) is set to 1. |
| 149 | * |
| 150 | * Due to some SPI controllers' shortcomings (Rockchip comes to |
| 151 | * mind...) we trasmit the 4 byte header without checking the byte |
| 152 | * transmitted by the TPM during the transaction's last byte. |
| 153 | * |
| 154 | * We know that cr50 is guaranteed to set the flow control bit to 0 |
| 155 | * during the header transfer, but real TPM2 might be fast enough not |
| 156 | * to require to stall the master, this would present an issue. |
| 157 | * crosbug.com/p/52132 has been opened to track this. |
| 158 | */ |
| 159 | tpm_if.xfer(tpm_if.slave, header.body, sizeof(header.body), NULL, 0); |
| 160 | |
| 161 | /* Now poll the bus until TPM removes the stall bit. */ |
| 162 | do { |
| 163 | tpm_if.xfer(tpm_if.slave, NULL, 0, &byte, 1); |
| 164 | } while (!(byte & 1)); |
| 165 | } |
| 166 | |
| 167 | /* |
| 168 | * Print out the contents of a buffer, if debug is enabled. Skip registers |
| 169 | * other than FIFO, unless debug_level_ is 2. |
| 170 | */ |
| 171 | static void trace_dump(const char *prefix, uint32_t reg, |
| 172 | size_t bytes, const uint8_t *buffer, |
| 173 | int force) |
| 174 | { |
| 175 | static char prev_prefix; |
| 176 | static unsigned prev_reg; |
| 177 | static int current_char; |
| 178 | const int BYTES_PER_LINE = 32; |
| 179 | |
| 180 | if (!force) { |
| 181 | if (!debug_level_) |
| 182 | return; |
| 183 | |
| 184 | if ((debug_level_ < 2) && (reg != TPM_DATA_FIFO_REG)) |
| 185 | return; |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * Do not print register address again if the last dump print was for |
| 190 | * that register. |
| 191 | */ |
| 192 | if ((prev_prefix != *prefix) || (prev_reg != reg)) { |
| 193 | prev_prefix = *prefix; |
| 194 | prev_reg = reg; |
| 195 | printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); |
| 196 | current_char = 0; |
| 197 | } |
| 198 | |
| 199 | if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { |
| 200 | /* |
| 201 | * This must be a regular register address, print the 32 bit |
| 202 | * value. |
| 203 | */ |
| 204 | printk(BIOS_DEBUG, " %8.8x", *(const uint32_t *)buffer); |
| 205 | } else { |
| 206 | int i; |
| 207 | |
| 208 | /* |
| 209 | * Data read from or written to FIFO or not in 4 byte |
| 210 | * quantiites is printed byte at a time. |
| 211 | */ |
| 212 | for (i = 0; i < bytes; i++) { |
| 213 | if (current_char && !(current_char % BYTES_PER_LINE)) { |
| 214 | printk(BIOS_DEBUG, "\n "); |
| 215 | current_char = 0; |
| 216 | } |
| 217 | current_char++; |
| 218 | printk(BIOS_DEBUG, " %2.2x", buffer[i]); |
| 219 | } |
| 220 | } |
| 221 | } |
| 222 | |
| 223 | /* |
| 224 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 225 | * write the actual bytes to the register. |
| 226 | */ |
| 227 | static void write_bytes(const void *buffer, size_t bytes) |
| 228 | { |
| 229 | tpm_if.xfer(tpm_if.slave, buffer, bytes, NULL, 0); |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 234 | * read the actual bytes from the register. |
| 235 | */ |
| 236 | static void read_bytes(void *buffer, size_t bytes) |
| 237 | { |
| 238 | tpm_if.xfer(tpm_if.slave, NULL, 0, buffer, bytes); |
| 239 | } |
| 240 | |
| 241 | /* |
| 242 | * To write a register, start transaction, transfer data to the TPM, deassert |
| 243 | * CS when done. |
| 244 | * |
| 245 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 246 | * failure. |
| 247 | */ |
| 248 | static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) |
| 249 | { |
| 250 | trace_dump("W", reg_number, bytes, buffer, 0); |
| 251 | start_transaction(false, bytes, reg_number); |
| 252 | write_bytes(buffer, bytes); |
| 253 | tpm_if.cs_deassert(tpm_if.slave); |
| 254 | return 1; |
| 255 | } |
| 256 | |
| 257 | /* |
| 258 | * To read a register, start transaction, transfer data from the TPM, deassert |
| 259 | * CS when done. |
| 260 | * |
| 261 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 262 | * failure. |
| 263 | */ |
| 264 | static int tpm2_read_reg(unsigned reg_number, void *buffer, size_t bytes) |
| 265 | { |
| 266 | start_transaction(true, bytes, reg_number); |
| 267 | read_bytes(buffer, bytes); |
| 268 | tpm_if.cs_deassert(tpm_if.slave); |
| 269 | trace_dump("R", reg_number, bytes, buffer, 0); |
| 270 | return 1; |
| 271 | } |
| 272 | |
| 273 | /* |
| 274 | * Status register is accessed often, wrap reading and writing it into |
| 275 | * dedicated functions. |
| 276 | */ |
| 277 | static int read_tpm_sts(uint32_t *status) |
| 278 | { |
| 279 | return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); |
| 280 | } |
| 281 | |
| 282 | static int write_tpm_sts(uint32_t status) |
| 283 | { |
| 284 | return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); |
| 285 | } |
| 286 | |
| 287 | /* |
| 288 | * The TPM may limit the transaction bytes count (burst count) below the 64 |
| 289 | * bytes max. The current value is available as a field of the status |
| 290 | * register. |
| 291 | */ |
| 292 | static uint32_t get_burst_count(void) |
| 293 | { |
| 294 | uint32_t status; |
| 295 | |
| 296 | read_tpm_sts(&status); |
| 297 | return (status >> burst_count_shift) & burst_count_mask; |
| 298 | } |
| 299 | |
| 300 | int tpm2_init(struct spi_slave *spi_if) |
| 301 | { |
| 302 | uint32_t did_vid, status; |
| 303 | uint8_t cmd; |
| 304 | |
| 305 | tpm_if.slave = spi_if; |
| 306 | |
| 307 | tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); |
| 308 | |
| 309 | /* Try claiming locality zero. */ |
| 310 | tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 311 | if ((cmd & (active_locality & tpm_reg_valid_sts)) == |
| 312 | (active_locality & tpm_reg_valid_sts)) { |
| 313 | /* |
| 314 | * Locality active - maybe reset line is not connected? |
| 315 | * Release the locality and try again |
| 316 | */ |
| 317 | cmd = active_locality; |
| 318 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 319 | tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 320 | } |
| 321 | |
| 322 | /* The tpm_establishment bit can be either set or not, ignore it. */ |
| 323 | if ((cmd & ~tpm_establishment) != tpm_reg_valid_sts) { |
| 324 | printk(BIOS_ERR, "invalid reset status: %#x\n", cmd); |
| 325 | return -1; |
| 326 | } |
| 327 | |
| 328 | cmd = request_use; |
| 329 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 330 | tpm2_read_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 331 | if ((cmd & ~tpm_establishment) != |
| 332 | (tpm_reg_valid_sts | active_locality)) { |
| 333 | printk(BIOS_ERR, "failed to claim locality 0, status: %#x\n", |
| 334 | cmd); |
| 335 | return -1; |
| 336 | } |
| 337 | |
| 338 | read_tpm_sts(&status); |
| 339 | if (((status >> tpm_family_shift) & tpm_family_mask) != |
| 340 | tpm_family_tpm2) { |
| 341 | printk(BIOS_ERR, "unexpected TPM family value, status: %#x\n", |
| 342 | status); |
| 343 | return -1; |
| 344 | } |
| 345 | |
| 346 | /* |
| 347 | * Locality claimed, read the revision value and set up the tpm_info |
| 348 | * structure. |
| 349 | */ |
| 350 | tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); |
| 351 | tpm_info.vendor_id = did_vid & 0xffff; |
| 352 | tpm_info.device_id = did_vid >> 16; |
| 353 | tpm_info.revision = cmd; |
| 354 | |
| 355 | printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", |
| 356 | tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | /* |
| 362 | * This is in seconds, certain TPM commands, like key generation, can take |
| 363 | * long time to complete. |
| 364 | * |
| 365 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 366 | * failure. |
| 367 | */ |
| 368 | #define MAX_STATUS_TIMEOUT 120 |
| 369 | static int wait_for_status(uint32_t status_mask, uint32_t status_expected) |
| 370 | { |
| 371 | uint32_t status; |
| 372 | struct stopwatch sw; |
| 373 | |
| 374 | stopwatch_init_usecs_expire(&sw, MAX_STATUS_TIMEOUT * 1000 * 1000); |
| 375 | do { |
| 376 | udelay(1000); |
| 377 | if (stopwatch_expired(&sw)) { |
| 378 | printk(BIOS_ERR, "failed to get expected status %x\n", |
| 379 | status_expected); |
| 380 | return false; |
| 381 | } |
| 382 | read_tpm_sts(&status); |
| 383 | } while ((status & status_mask) != status_expected); |
| 384 | |
| 385 | return 1; |
| 386 | } |
| 387 | |
| 388 | enum fifo_transfer_direction { |
| 389 | fifo_transmit = 0, |
| 390 | fifo_receive = 1 |
| 391 | }; |
| 392 | |
| 393 | /* Union allows to avoid casting away 'const' on transmit buffers. */ |
| 394 | union fifo_transfer_buffer { |
| 395 | uint8_t *rx_buffer; |
| 396 | const uint8_t *tx_buffer; |
| 397 | }; |
| 398 | |
| 399 | /* |
| 400 | * Transfer requested number of bytes to or from TPM FIFO, accounting for the |
| 401 | * current burst count value. |
| 402 | */ |
| 403 | static void fifo_transfer(size_t transfer_size, |
| 404 | union fifo_transfer_buffer buffer, |
| 405 | enum fifo_transfer_direction direction) |
| 406 | { |
| 407 | size_t transaction_size; |
| 408 | size_t burst_count; |
| 409 | size_t handled_so_far = 0; |
| 410 | |
| 411 | do { |
| 412 | do { |
| 413 | /* Could be zero when TPM is busy. */ |
| 414 | burst_count = get_burst_count(); |
| 415 | } while (!burst_count); |
| 416 | |
| 417 | transaction_size = transfer_size - handled_so_far; |
| 418 | transaction_size = MIN(transaction_size, burst_count); |
| 419 | |
| 420 | /* |
| 421 | * The SPI frame header does not allow to pass more than 64 |
| 422 | * bytes. |
| 423 | */ |
| 424 | transaction_size = MIN(transaction_size, 64); |
| 425 | |
| 426 | if (direction == fifo_receive) |
| 427 | tpm2_read_reg(TPM_DATA_FIFO_REG, |
| 428 | buffer.rx_buffer + handled_so_far, |
| 429 | transaction_size); |
| 430 | else |
| 431 | tpm2_write_reg(TPM_DATA_FIFO_REG, |
| 432 | buffer.tx_buffer + handled_so_far, |
| 433 | transaction_size); |
| 434 | |
| 435 | handled_so_far += transaction_size; |
| 436 | |
| 437 | } while (handled_so_far != transfer_size); |
| 438 | } |
| 439 | |
| 440 | size_t tpm2_process_command(const void *tpm2_command, size_t command_size, |
| 441 | void *tpm2_response, size_t max_response) |
| 442 | { |
| 443 | uint32_t status; |
| 444 | uint32_t expected_status_bits; |
| 445 | size_t payload_size; |
| 446 | size_t bytes_to_go; |
| 447 | const uint8_t *cmd_body = tpm2_command; |
| 448 | uint8_t *rsp_body = tpm2_response; |
| 449 | union fifo_transfer_buffer fifo_buffer; |
| 450 | const int HEADER_SIZE = 6; |
| 451 | |
| 452 | /* Skip the two byte tag, read the size field. */ |
| 453 | payload_size = read_be32(cmd_body + 2); |
| 454 | |
| 455 | /* Sanity check. */ |
| 456 | if (payload_size != command_size) { |
| 457 | printk(BIOS_ERR, |
| 458 | "Command size mismatch: encoded %zd != requested %zd\n", |
| 459 | payload_size, command_size); |
| 460 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 461 | printk(BIOS_DEBUG, "\n"); |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | /* Let the TPM know that the command is coming. */ |
| 466 | write_tpm_sts(command_ready); |
| 467 | |
| 468 | /* |
| 469 | * Tpm commands and responses written to and read from the FIFO |
| 470 | * register (0x24) are datagrams of variable size, prepended by a 6 |
| 471 | * byte header. |
| 472 | * |
| 473 | * The specification description of the state machine is a bit vague, |
| 474 | * but from experience it looks like there is no need to wait for the |
| 475 | * sts.expect bit to be set, at least with the 9670 and cr50 devices. |
| 476 | * Just write the command into FIFO, making sure not to exceed the |
| 477 | * burst count or the maximum PDU size, whatever is smaller. |
| 478 | */ |
| 479 | fifo_buffer.tx_buffer = cmd_body; |
| 480 | fifo_transfer(command_size, fifo_buffer, fifo_transmit); |
| 481 | |
| 482 | /* Now tell the TPM it can start processing the command. */ |
| 483 | write_tpm_sts(tpm_go); |
| 484 | |
| 485 | /* Now wait for it to report that the response is ready. */ |
| 486 | expected_status_bits = sts_valid | data_avail; |
| 487 | if (!wait_for_status(expected_status_bits, expected_status_bits)) { |
| 488 | /* |
| 489 | * If timed out, which should never happen, let's at least |
| 490 | * print out the offending command. |
| 491 | */ |
| 492 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 493 | printk(BIOS_DEBUG, "\n"); |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | /* |
| 498 | * The response is ready, let's read it. First we read the FIFO |
| 499 | * payload header, to see how much data to expect. The response header |
| 500 | * size is fixed to six bytes, the total payload size is stored in |
| 501 | * network order in the last four bytes. |
| 502 | */ |
| 503 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body, HEADER_SIZE); |
| 504 | |
| 505 | /* Find out the total payload size, skipping the two byte tag. */ |
| 506 | payload_size = read_be32(rsp_body + 2); |
| 507 | |
| 508 | if (payload_size > max_response) { |
| 509 | /* |
| 510 | * TODO(vbendeb): at least drain the FIFO here or somehow let |
| 511 | * the TPM know that the response can be dropped. |
| 512 | */ |
| 513 | printk(BIOS_ERR, " tpm response too long (%zd bytes)", |
| 514 | payload_size); |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | /* |
| 519 | * Now let's read all but the last byte in the FIFO to make sure the |
| 520 | * status register is showing correct flow control bits: 'more data' |
| 521 | * until the last byte and then 'no more data' once the last byte is |
| 522 | * read. |
| 523 | */ |
| 524 | bytes_to_go = payload_size - 1 - HEADER_SIZE; |
| 525 | fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; |
| 526 | fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); |
| 527 | |
| 528 | /* Verify that there is still data to read. */ |
| 529 | read_tpm_sts(&status); |
| 530 | if ((status & expected_status_bits) != expected_status_bits) { |
| 531 | printk(BIOS_ERR, "unexpected intermediate status %#x\n", |
| 532 | status); |
| 533 | return 0; |
| 534 | } |
| 535 | |
| 536 | /* Read the last byte of the PDU. */ |
| 537 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body + payload_size - 1, 1); |
| 538 | |
| 539 | /* Terminate the dump, if enabled. */ |
| 540 | if (debug_level_) |
| 541 | printk(BIOS_DEBUG, "\n"); |
| 542 | |
| 543 | /* Verify that 'data available' is not asseretd any more. */ |
| 544 | read_tpm_sts(&status); |
| 545 | if ((status & expected_status_bits) != sts_valid) { |
| 546 | printk(BIOS_ERR, "unexpected final status %#x\n", status); |
| 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | /* Move the TPM back to idle state. */ |
| 551 | write_tpm_sts(command_ready); |
| 552 | |
| 553 | return payload_size; |
| 554 | } |