Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 The Chromium OS Authors. All rights reserved. |
| 3 | * Use of this source code is governed by a BSD-style license that can be |
| 4 | * found in the LICENSE file. |
| 5 | * |
| 6 | * This is a driver for a SPI interfaced TPM2 device. |
| 7 | * |
| 8 | * It assumes that the required SPI interface has been initialized before the |
| 9 | * driver is started. A 'sruct spi_slave' pointer passed at initialization is |
| 10 | * used to direct traffic to the correct SPI interface. This dirver does not |
| 11 | * provide a way to instantiate multiple TPM devices. Also, to keep things |
| 12 | * simple, the driver unconditionally uses of TPM locality zero. |
| 13 | * |
| 14 | * References to documentation are based on the TCG issued "TPM Profile (PTP) |
| 15 | * Specification Revision 00.43". |
| 16 | */ |
| 17 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 18 | #include <arch/early_variables.h> |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 19 | #include <assert.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 20 | #include <commonlib/endian.h> |
| 21 | #include <console/console.h> |
| 22 | #include <delay.h> |
| 23 | #include <endian.h> |
| 24 | #include <string.h> |
| 25 | #include <timer.h> |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 26 | #include <tpm.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 27 | |
| 28 | #include "tpm.h" |
| 29 | |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 30 | #define TPM_LOCALITY_0_SPI_BASE 0x00d40000 |
| 31 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 32 | /* Assorted TPM2 registers for interface type FIFO. */ |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 33 | #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) |
| 34 | #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) |
| 35 | #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) |
| 36 | #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) |
| 37 | #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 38 | #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 39 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 40 | /* SPI slave structure for TPM device. */ |
| 41 | static struct spi_slave g_spi_slave CAR_GLOBAL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 42 | |
| 43 | /* Cached TPM device identification. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 44 | static struct tpm2_info g_tpm_info CAR_GLOBAL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of |
| 48 | * debug traces. Right now it is either 0 or 1. |
| 49 | */ |
| 50 | static const int debug_level_ = CONFIG_DEBUG_TPM; |
| 51 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 52 | /* |
| 53 | * SPI frame header for TPM transactions is 4 bytes in size, it is described |
| 54 | * in section "6.4.6 Spi Bit Protocol". |
| 55 | */ |
| 56 | typedef struct { |
| 57 | unsigned char body[4]; |
| 58 | } spi_frame_header; |
| 59 | |
| 60 | void tpm2_get_info(struct tpm2_info *info) |
| 61 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 62 | *info = car_get_var(g_tpm_info); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 63 | } |
| 64 | |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 65 | __attribute__((weak)) int tis_plat_irq_status(void) |
| 66 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 67 | static int warning_displayed CAR_GLOBAL; |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 68 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 69 | if (!car_get_var(warning_displayed)) { |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 70 | printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 10ms to wait on Cr50!\n"); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 71 | car_set_var(warning_displayed, 1); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 72 | } |
| 73 | mdelay(10); |
| 74 | |
| 75 | return 1; |
| 76 | } |
| 77 | |
| 78 | /* |
| 79 | * TPM may trigger a irq after finish processing previous transfer. |
| 80 | * Waiting for this irq to sync tpm status. |
| 81 | * |
| 82 | * Returns 1 on success, 0 on failure (timeout). |
| 83 | */ |
| 84 | static int tpm_sync(void) |
| 85 | { |
| 86 | struct stopwatch sw; |
| 87 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 88 | stopwatch_init_msecs_expire(&sw, 10); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 89 | while (!tis_plat_irq_status()) { |
| 90 | if (stopwatch_expired(&sw)) { |
| 91 | printk(BIOS_ERR, "Timeout wait for tpm irq!\n"); |
| 92 | return 0; |
| 93 | } |
| 94 | } |
| 95 | return 1; |
| 96 | } |
| 97 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 98 | /* |
| 99 | * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte |
| 100 | * header is sent to the TPM, the master waits til TPM is ready to continue. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 101 | * |
| 102 | * Returns 1 on success, 0 on failure (TPM SPI flow control timeout.) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 103 | */ |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 104 | static int start_transaction(int read_write, size_t bytes, unsigned addr) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 105 | { |
| 106 | spi_frame_header header; |
| 107 | uint8_t byte; |
| 108 | int i; |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 109 | struct stopwatch sw; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 110 | static int tpm_sync_needed CAR_GLOBAL; |
| 111 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 112 | |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 113 | /* Wait for tpm to finish previous transaction if needed */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 114 | if (car_get_var(tpm_sync_needed)) |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 115 | tpm_sync(); |
| 116 | else |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 117 | car_set_var(tpm_sync_needed, 1); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 118 | |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 119 | /* Try to wake cr50 if it is asleep. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 120 | spi_claim_bus(spi_slave); |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 121 | udelay(1); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 122 | spi_release_bus(spi_slave); |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 123 | udelay(100); |
| 124 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 125 | /* |
| 126 | * The first byte of the frame header encodes the transaction type |
| 127 | * (read or write) and transfer size (set to lentgh - 1), limited to |
| 128 | * 64 bytes. |
| 129 | */ |
| 130 | header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); |
| 131 | |
| 132 | /* The rest of the frame header is the TPM register address. */ |
| 133 | for (i = 0; i < 3; i++) |
| 134 | header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; |
| 135 | |
| 136 | /* CS assert wakes up the slave. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 137 | spi_claim_bus(spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * The TCG TPM over SPI specification introduces the notion of SPI |
| 141 | * flow control (Section "6.4.5 Flow Control"). |
| 142 | * |
| 143 | * Again, the slave (TPM device) expects each transaction to start |
| 144 | * with a 4 byte header trasmitted by master. The header indicates if |
| 145 | * the master needs to read or write a register, and the register |
| 146 | * address. |
| 147 | * |
| 148 | * If the slave needs to stall the transaction (for instance it is not |
| 149 | * ready to send the register value to the master), it sets the MOSI |
| 150 | * line to 0 during the last clock of the 4 byte header. In this case |
| 151 | * the master is supposed to start polling the SPI bus, one byte at |
| 152 | * time, until the last bit in the received byte (transferred during |
| 153 | * the last clock of the byte) is set to 1. |
| 154 | * |
| 155 | * Due to some SPI controllers' shortcomings (Rockchip comes to |
| 156 | * mind...) we trasmit the 4 byte header without checking the byte |
| 157 | * transmitted by the TPM during the transaction's last byte. |
| 158 | * |
| 159 | * We know that cr50 is guaranteed to set the flow control bit to 0 |
| 160 | * during the header transfer, but real TPM2 might be fast enough not |
| 161 | * to require to stall the master, this would present an issue. |
| 162 | * crosbug.com/p/52132 has been opened to track this. |
| 163 | */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 164 | spi_xfer(spi_slave, header.body, sizeof(header.body), NULL, 0); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 165 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 166 | /* |
| 167 | * Now poll the bus until TPM removes the stall bit. Give it up to 100 |
| 168 | * ms to sort it out - it could be saving stuff in nvram at some |
| 169 | * point. |
| 170 | */ |
| 171 | stopwatch_init_msecs_expire(&sw, 100); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 172 | do { |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 173 | if (stopwatch_expired(&sw)) { |
| 174 | printk(BIOS_ERR, "TPM flow control failure\n"); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 175 | spi_release_bus(spi_slave); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 176 | return 0; |
| 177 | } |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 178 | spi_xfer(spi_slave, NULL, 0, &byte, 1); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 179 | } while (!(byte & 1)); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 180 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 181 | } |
| 182 | |
| 183 | /* |
| 184 | * Print out the contents of a buffer, if debug is enabled. Skip registers |
| 185 | * other than FIFO, unless debug_level_ is 2. |
| 186 | */ |
| 187 | static void trace_dump(const char *prefix, uint32_t reg, |
| 188 | size_t bytes, const uint8_t *buffer, |
| 189 | int force) |
| 190 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 191 | static char prev_prefix CAR_GLOBAL; |
| 192 | static unsigned prev_reg CAR_GLOBAL; |
| 193 | static int current_char CAR_GLOBAL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 194 | const int BYTES_PER_LINE = 32; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 195 | int *current_char_ptr = car_get_var_ptr(¤t_char); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 196 | |
| 197 | if (!force) { |
| 198 | if (!debug_level_) |
| 199 | return; |
| 200 | |
| 201 | if ((debug_level_ < 2) && (reg != TPM_DATA_FIFO_REG)) |
| 202 | return; |
| 203 | } |
| 204 | |
| 205 | /* |
| 206 | * Do not print register address again if the last dump print was for |
| 207 | * that register. |
| 208 | */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 209 | if ((car_get_var(prev_prefix) != *prefix) || |
| 210 | (car_get_var(prev_reg) != reg)) { |
| 211 | car_set_var(prev_prefix, *prefix); |
| 212 | car_set_var(prev_reg, reg); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 213 | printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 214 | *current_char_ptr = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { |
| 218 | /* |
| 219 | * This must be a regular register address, print the 32 bit |
| 220 | * value. |
| 221 | */ |
| 222 | printk(BIOS_DEBUG, " %8.8x", *(const uint32_t *)buffer); |
| 223 | } else { |
| 224 | int i; |
| 225 | |
| 226 | /* |
| 227 | * Data read from or written to FIFO or not in 4 byte |
| 228 | * quantiites is printed byte at a time. |
| 229 | */ |
| 230 | for (i = 0; i < bytes; i++) { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 231 | if (*current_char_ptr && |
| 232 | !(*current_char_ptr % BYTES_PER_LINE)) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 233 | printk(BIOS_DEBUG, "\n "); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 234 | *current_char_ptr = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 235 | } |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 236 | (*current_char_ptr)++; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 237 | printk(BIOS_DEBUG, " %2.2x", buffer[i]); |
| 238 | } |
| 239 | } |
| 240 | } |
| 241 | |
| 242 | /* |
| 243 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 244 | * write the actual bytes to the register. |
| 245 | */ |
| 246 | static void write_bytes(const void *buffer, size_t bytes) |
| 247 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 248 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
| 249 | spi_xfer(spi_slave, buffer, bytes, NULL, 0); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | /* |
| 253 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 254 | * read the actual bytes from the register. |
| 255 | */ |
| 256 | static void read_bytes(void *buffer, size_t bytes) |
| 257 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 258 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
| 259 | spi_xfer(spi_slave, NULL, 0, buffer, bytes); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | /* |
| 263 | * To write a register, start transaction, transfer data to the TPM, deassert |
| 264 | * CS when done. |
| 265 | * |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 266 | * Returns one to indicate success, zero to indicate failure. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 267 | */ |
| 268 | static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) |
| 269 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 270 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 271 | trace_dump("W", reg_number, bytes, buffer, 0); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 272 | if (!start_transaction(false, bytes, reg_number)) |
| 273 | return 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 274 | write_bytes(buffer, bytes); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 275 | spi_release_bus(spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 276 | return 1; |
| 277 | } |
| 278 | |
| 279 | /* |
| 280 | * To read a register, start transaction, transfer data from the TPM, deassert |
| 281 | * CS when done. |
| 282 | * |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 283 | * Returns one to indicate success, zero to indicate failure. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 284 | */ |
| 285 | static int tpm2_read_reg(unsigned reg_number, void *buffer, size_t bytes) |
| 286 | { |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 287 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 288 | if (!start_transaction(true, bytes, reg_number)) { |
| 289 | memset(buffer, 0, bytes); |
| 290 | return 0; |
| 291 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 292 | read_bytes(buffer, bytes); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 293 | spi_release_bus(spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 294 | trace_dump("R", reg_number, bytes, buffer, 0); |
| 295 | return 1; |
| 296 | } |
| 297 | |
| 298 | /* |
| 299 | * Status register is accessed often, wrap reading and writing it into |
| 300 | * dedicated functions. |
| 301 | */ |
| 302 | static int read_tpm_sts(uint32_t *status) |
| 303 | { |
| 304 | return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); |
| 305 | } |
| 306 | |
| 307 | static int write_tpm_sts(uint32_t status) |
| 308 | { |
| 309 | return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); |
| 310 | } |
| 311 | |
| 312 | /* |
| 313 | * The TPM may limit the transaction bytes count (burst count) below the 64 |
| 314 | * bytes max. The current value is available as a field of the status |
| 315 | * register. |
| 316 | */ |
| 317 | static uint32_t get_burst_count(void) |
| 318 | { |
| 319 | uint32_t status; |
| 320 | |
| 321 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 322 | return (status & TPM_STS_BURST_COUNT_MASK) >> TPM_STS_BURST_COUNT_SHIFT; |
| 323 | } |
| 324 | |
| 325 | static uint8_t tpm2_read_access_reg(void) |
| 326 | { |
| 327 | uint8_t access; |
| 328 | tpm2_read_reg(TPM_ACCESS_REG, &access, sizeof(access)); |
| 329 | /* We do not care about access establishment bit state. Ignore it. */ |
| 330 | return access & ~TPM_ACCESS_ESTABLISHMENT; |
| 331 | } |
| 332 | |
| 333 | static void tpm2_write_access_reg(uint8_t cmd) |
| 334 | { |
| 335 | /* Writes to access register can set only 1 bit at a time. */ |
| 336 | assert (!(cmd & (cmd - 1))); |
| 337 | |
| 338 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 339 | } |
| 340 | |
| 341 | static int tpm2_claim_locality(void) |
| 342 | { |
| 343 | uint8_t access; |
| 344 | |
| 345 | access = tpm2_read_access_reg(); |
| 346 | /* |
| 347 | * If active locality is set (maybe reset line is not connected?), |
| 348 | * release the locality and try again. |
| 349 | */ |
| 350 | if (access & TPM_ACCESS_ACTIVE_LOCALITY) { |
| 351 | tpm2_write_access_reg(TPM_ACCESS_ACTIVE_LOCALITY); |
| 352 | access = tpm2_read_access_reg(); |
| 353 | } |
| 354 | |
| 355 | if (access != TPM_ACCESS_VALID) { |
| 356 | printk(BIOS_ERR, "Invalid reset status: %#x\n", access); |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | tpm2_write_access_reg(TPM_ACCESS_REQUEST_USE); |
| 361 | access = tpm2_read_access_reg(); |
| 362 | if (access != (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) { |
| 363 | printk(BIOS_ERR, "Failed to claim locality 0, status: %#x\n", |
| 364 | access); |
| 365 | return 0; |
| 366 | } |
| 367 | |
| 368 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 369 | } |
| 370 | |
| 371 | int tpm2_init(struct spi_slave *spi_if) |
| 372 | { |
| 373 | uint32_t did_vid, status; |
| 374 | uint8_t cmd; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 375 | struct tpm2_info *tpm_info = car_get_var_ptr(&g_tpm_info); |
| 376 | struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 377 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 378 | memcpy(spi_slave, spi_if, sizeof(*spi_if)); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 379 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 380 | /* |
| 381 | * It is enough to check the first register read error status to bail |
| 382 | * out in case of malfunctioning TPM. |
| 383 | */ |
| 384 | if (!tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid))) |
| 385 | return -1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 386 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 387 | /* Claim locality 0. */ |
| 388 | if (!tpm2_claim_locality()) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 389 | return -1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 390 | |
| 391 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 392 | if ((status & TPM_STS_FAMILY_MASK) != TPM_STS_FAMILY_TPM_2_0) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 393 | printk(BIOS_ERR, "unexpected TPM family value, status: %#x\n", |
| 394 | status); |
| 395 | return -1; |
| 396 | } |
| 397 | |
| 398 | /* |
| 399 | * Locality claimed, read the revision value and set up the tpm_info |
| 400 | * structure. |
| 401 | */ |
| 402 | tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 403 | tpm_info->vendor_id = did_vid & 0xffff; |
| 404 | tpm_info->device_id = did_vid >> 16; |
| 405 | tpm_info->revision = cmd; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 406 | |
| 407 | printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 408 | tpm_info->vendor_id, tpm_info->device_id, tpm_info->revision); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 409 | |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 410 | /* Let's report device FW version if available. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 411 | if (tpm_info->vendor_id == 0x1ae0) { |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 412 | int chunk_count = 0; |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 413 | size_t chunk_size; |
| 414 | /* |
| 415 | * let's read 50 bytes at a time; leave room for the trailing |
| 416 | * zero. |
| 417 | */ |
| 418 | char vstr[51]; |
| 419 | |
| 420 | chunk_size = sizeof(vstr) - 1; |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 421 | |
| 422 | printk(BIOS_INFO, "Firmware version: "); |
| 423 | |
| 424 | /* |
| 425 | * Does not really matter what's written, this just makes sure |
| 426 | * the version is reported from the beginning. |
| 427 | */ |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 428 | tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 429 | |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 430 | /* Print it out in sizeof(vstr) - 1 byte chunks. */ |
| 431 | vstr[chunk_size] = 0; |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 432 | do { |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 433 | tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 434 | printk(BIOS_INFO, "%s", vstr); |
| 435 | |
| 436 | /* |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 437 | * While string is not over, and is no longer than 300 |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 438 | * characters. |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 439 | */ |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 440 | } while (vstr[chunk_size - 1] && |
| 441 | (chunk_count++ < (300 / chunk_size))); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 442 | |
| 443 | printk(BIOS_INFO, "\n"); |
| 444 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | /* |
| 449 | * This is in seconds, certain TPM commands, like key generation, can take |
| 450 | * long time to complete. |
| 451 | * |
| 452 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 453 | * failure. |
| 454 | */ |
| 455 | #define MAX_STATUS_TIMEOUT 120 |
| 456 | static int wait_for_status(uint32_t status_mask, uint32_t status_expected) |
| 457 | { |
| 458 | uint32_t status; |
| 459 | struct stopwatch sw; |
| 460 | |
| 461 | stopwatch_init_usecs_expire(&sw, MAX_STATUS_TIMEOUT * 1000 * 1000); |
| 462 | do { |
| 463 | udelay(1000); |
| 464 | if (stopwatch_expired(&sw)) { |
| 465 | printk(BIOS_ERR, "failed to get expected status %x\n", |
| 466 | status_expected); |
| 467 | return false; |
| 468 | } |
| 469 | read_tpm_sts(&status); |
| 470 | } while ((status & status_mask) != status_expected); |
| 471 | |
| 472 | return 1; |
| 473 | } |
| 474 | |
| 475 | enum fifo_transfer_direction { |
| 476 | fifo_transmit = 0, |
| 477 | fifo_receive = 1 |
| 478 | }; |
| 479 | |
| 480 | /* Union allows to avoid casting away 'const' on transmit buffers. */ |
| 481 | union fifo_transfer_buffer { |
| 482 | uint8_t *rx_buffer; |
| 483 | const uint8_t *tx_buffer; |
| 484 | }; |
| 485 | |
| 486 | /* |
| 487 | * Transfer requested number of bytes to or from TPM FIFO, accounting for the |
| 488 | * current burst count value. |
| 489 | */ |
| 490 | static void fifo_transfer(size_t transfer_size, |
| 491 | union fifo_transfer_buffer buffer, |
| 492 | enum fifo_transfer_direction direction) |
| 493 | { |
| 494 | size_t transaction_size; |
| 495 | size_t burst_count; |
| 496 | size_t handled_so_far = 0; |
| 497 | |
| 498 | do { |
| 499 | do { |
| 500 | /* Could be zero when TPM is busy. */ |
| 501 | burst_count = get_burst_count(); |
| 502 | } while (!burst_count); |
| 503 | |
| 504 | transaction_size = transfer_size - handled_so_far; |
| 505 | transaction_size = MIN(transaction_size, burst_count); |
| 506 | |
| 507 | /* |
| 508 | * The SPI frame header does not allow to pass more than 64 |
| 509 | * bytes. |
| 510 | */ |
| 511 | transaction_size = MIN(transaction_size, 64); |
| 512 | |
| 513 | if (direction == fifo_receive) |
| 514 | tpm2_read_reg(TPM_DATA_FIFO_REG, |
| 515 | buffer.rx_buffer + handled_so_far, |
| 516 | transaction_size); |
| 517 | else |
| 518 | tpm2_write_reg(TPM_DATA_FIFO_REG, |
| 519 | buffer.tx_buffer + handled_so_far, |
| 520 | transaction_size); |
| 521 | |
| 522 | handled_so_far += transaction_size; |
| 523 | |
| 524 | } while (handled_so_far != transfer_size); |
| 525 | } |
| 526 | |
| 527 | size_t tpm2_process_command(const void *tpm2_command, size_t command_size, |
| 528 | void *tpm2_response, size_t max_response) |
| 529 | { |
| 530 | uint32_t status; |
| 531 | uint32_t expected_status_bits; |
| 532 | size_t payload_size; |
| 533 | size_t bytes_to_go; |
| 534 | const uint8_t *cmd_body = tpm2_command; |
| 535 | uint8_t *rsp_body = tpm2_response; |
| 536 | union fifo_transfer_buffer fifo_buffer; |
| 537 | const int HEADER_SIZE = 6; |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 538 | struct tpm2_info *tpm_info = car_get_var_ptr(&g_tpm_info); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 539 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 540 | /* Do not try using an uninitialized TPM. */ |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 541 | if (!tpm_info->vendor_id) |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 542 | return 0; |
| 543 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 544 | /* Skip the two byte tag, read the size field. */ |
| 545 | payload_size = read_be32(cmd_body + 2); |
| 546 | |
| 547 | /* Sanity check. */ |
| 548 | if (payload_size != command_size) { |
| 549 | printk(BIOS_ERR, |
| 550 | "Command size mismatch: encoded %zd != requested %zd\n", |
| 551 | payload_size, command_size); |
| 552 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 553 | printk(BIOS_DEBUG, "\n"); |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | /* Let the TPM know that the command is coming. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 558 | write_tpm_sts(TPM_STS_COMMAND_READY); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 559 | |
| 560 | /* |
| 561 | * Tpm commands and responses written to and read from the FIFO |
| 562 | * register (0x24) are datagrams of variable size, prepended by a 6 |
| 563 | * byte header. |
| 564 | * |
| 565 | * The specification description of the state machine is a bit vague, |
| 566 | * but from experience it looks like there is no need to wait for the |
| 567 | * sts.expect bit to be set, at least with the 9670 and cr50 devices. |
| 568 | * Just write the command into FIFO, making sure not to exceed the |
| 569 | * burst count or the maximum PDU size, whatever is smaller. |
| 570 | */ |
| 571 | fifo_buffer.tx_buffer = cmd_body; |
| 572 | fifo_transfer(command_size, fifo_buffer, fifo_transmit); |
| 573 | |
| 574 | /* Now tell the TPM it can start processing the command. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 575 | write_tpm_sts(TPM_STS_GO); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 576 | |
| 577 | /* Now wait for it to report that the response is ready. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 578 | expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 579 | if (!wait_for_status(expected_status_bits, expected_status_bits)) { |
| 580 | /* |
| 581 | * If timed out, which should never happen, let's at least |
| 582 | * print out the offending command. |
| 583 | */ |
| 584 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 585 | printk(BIOS_DEBUG, "\n"); |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | /* |
| 590 | * The response is ready, let's read it. First we read the FIFO |
| 591 | * payload header, to see how much data to expect. The response header |
| 592 | * size is fixed to six bytes, the total payload size is stored in |
| 593 | * network order in the last four bytes. |
| 594 | */ |
| 595 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body, HEADER_SIZE); |
| 596 | |
| 597 | /* Find out the total payload size, skipping the two byte tag. */ |
| 598 | payload_size = read_be32(rsp_body + 2); |
| 599 | |
| 600 | if (payload_size > max_response) { |
| 601 | /* |
| 602 | * TODO(vbendeb): at least drain the FIFO here or somehow let |
| 603 | * the TPM know that the response can be dropped. |
| 604 | */ |
| 605 | printk(BIOS_ERR, " tpm response too long (%zd bytes)", |
| 606 | payload_size); |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | /* |
| 611 | * Now let's read all but the last byte in the FIFO to make sure the |
| 612 | * status register is showing correct flow control bits: 'more data' |
| 613 | * until the last byte and then 'no more data' once the last byte is |
| 614 | * read. |
| 615 | */ |
| 616 | bytes_to_go = payload_size - 1 - HEADER_SIZE; |
| 617 | fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; |
| 618 | fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); |
| 619 | |
| 620 | /* Verify that there is still data to read. */ |
| 621 | read_tpm_sts(&status); |
| 622 | if ((status & expected_status_bits) != expected_status_bits) { |
| 623 | printk(BIOS_ERR, "unexpected intermediate status %#x\n", |
| 624 | status); |
| 625 | return 0; |
| 626 | } |
| 627 | |
| 628 | /* Read the last byte of the PDU. */ |
| 629 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body + payload_size - 1, 1); |
| 630 | |
| 631 | /* Terminate the dump, if enabled. */ |
| 632 | if (debug_level_) |
| 633 | printk(BIOS_DEBUG, "\n"); |
| 634 | |
| 635 | /* Verify that 'data available' is not asseretd any more. */ |
| 636 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 637 | if ((status & expected_status_bits) != TPM_STS_VALID) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 638 | printk(BIOS_ERR, "unexpected final status %#x\n", status); |
| 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | /* Move the TPM back to idle state. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame^] | 643 | write_tpm_sts(TPM_STS_COMMAND_READY); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 644 | |
| 645 | return payload_size; |
| 646 | } |