Patrick Georgi | 593124d | 2020-05-10 19:44:08 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* This is a driver for a SPI interfaced TPM2 device. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 3 | * |
| 4 | * It assumes that the required SPI interface has been initialized before the |
| 5 | * driver is started. A 'sruct spi_slave' pointer passed at initialization is |
| 6 | * used to direct traffic to the correct SPI interface. This dirver does not |
| 7 | * provide a way to instantiate multiple TPM devices. Also, to keep things |
| 8 | * simple, the driver unconditionally uses of TPM locality zero. |
| 9 | * |
| 10 | * References to documentation are based on the TCG issued "TPM Profile (PTP) |
| 11 | * Specification Revision 00.43". |
| 12 | */ |
| 13 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 14 | #include <assert.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 15 | #include <commonlib/endian.h> |
| 16 | #include <console/console.h> |
| 17 | #include <delay.h> |
| 18 | #include <endian.h> |
| 19 | #include <string.h> |
| 20 | #include <timer.h> |
Philipp Deppenwiese | d88fb36 | 2017-10-18 20:26:18 +0200 | [diff] [blame] | 21 | #include <security/tpm/tis.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 22 | |
| 23 | #include "tpm.h" |
| 24 | |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 25 | #define TPM_LOCALITY_0_SPI_BASE 0x00d40000 |
| 26 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 27 | /* Assorted TPM2 registers for interface type FIFO. */ |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 28 | #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) |
| 29 | #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) |
| 30 | #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) |
| 31 | #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) |
| 32 | #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 33 | #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 34 | #define CR50_BOARD_CFG (TPM_LOCALITY_0_SPI_BASE + 0xfe0) |
| 35 | |
| 36 | #define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U |
| 37 | #define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU |
| 38 | |
| 39 | #define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U |
| 40 | #define CR50_BOARD_CFG_VALUE \ |
| 41 | (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ |
| 42 | ? CR50_BOARD_CFG_100US_READY_PULSE : 0) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 43 | |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 44 | #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ |
| 45 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 46 | /* SPI slave structure for TPM device. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 47 | static struct spi_slave spi_slave; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 48 | |
| 49 | /* Cached TPM device identification. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 50 | static struct tpm2_info tpm_info; |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 51 | static struct cr50_firmware_version cr50_firmware_version; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 52 | |
| 53 | /* |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 54 | * TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 55 | * debug traces. Right now it is either 0 or 1. |
| 56 | */ |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 57 | static const int debug_level_ = CONFIG(DEBUG_TPM); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 58 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 59 | /* |
| 60 | * SPI frame header for TPM transactions is 4 bytes in size, it is described |
| 61 | * in section "6.4.6 Spi Bit Protocol". |
| 62 | */ |
| 63 | typedef struct { |
| 64 | unsigned char body[4]; |
| 65 | } spi_frame_header; |
| 66 | |
| 67 | void tpm2_get_info(struct tpm2_info *info) |
| 68 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 69 | *info = tpm_info; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 70 | } |
| 71 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 72 | __weak int tis_plat_irq_status(void) |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 73 | { |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 74 | static int warning_displayed; |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 75 | |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 76 | if (!warning_displayed) { |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 77 | printk(BIOS_WARNING, "WARNING: tis_plat_irq_status() not implemented, wasting 10ms to wait on Cr50!\n"); |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 78 | warning_displayed = 1; |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 79 | } |
| 80 | mdelay(10); |
| 81 | |
| 82 | return 1; |
| 83 | } |
| 84 | |
| 85 | /* |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 86 | * TPM may trigger a IRQ after finish processing previous transfer. |
| 87 | * Waiting for this IRQ to sync TPM status. |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 88 | * |
| 89 | * Returns 1 on success, 0 on failure (timeout). |
| 90 | */ |
| 91 | static int tpm_sync(void) |
| 92 | { |
| 93 | struct stopwatch sw; |
| 94 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 95 | stopwatch_init_msecs_expire(&sw, 10); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 96 | while (!tis_plat_irq_status()) { |
| 97 | if (stopwatch_expired(&sw)) { |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 98 | printk(BIOS_ERR, "Timeout wait for TPM IRQ!\n"); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 99 | return 0; |
| 100 | } |
| 101 | } |
| 102 | return 1; |
| 103 | } |
| 104 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 105 | /* |
| 106 | * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte |
| 107 | * header is sent to the TPM, the master waits til TPM is ready to continue. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 108 | * |
| 109 | * Returns 1 on success, 0 on failure (TPM SPI flow control timeout.) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 110 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 111 | static int start_transaction(int read_write, size_t bytes, unsigned int addr) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 112 | { |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 113 | spi_frame_header header, header_resp; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 114 | uint8_t byte; |
| 115 | int i; |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 116 | int ret; |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 117 | struct stopwatch sw; |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 118 | static int tpm_sync_needed; |
| 119 | static struct stopwatch wake_up_sw; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 120 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 121 | if (CONFIG(TPM_CR50)) { |
Vadim Bendebury | 3b62d6b | 2017-10-30 18:29:03 -0700 | [diff] [blame] | 122 | /* |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 123 | * First Cr50 access in each coreboot stage where TPM is used will be |
| 124 | * prepended by a wake up pulse on the CS line. |
Vadim Bendebury | 3b62d6b | 2017-10-30 18:29:03 -0700 | [diff] [blame] | 125 | */ |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 126 | int wakeup_needed = 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 127 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 128 | /* Wait for TPM to finish previous transaction if needed */ |
| 129 | if (tpm_sync_needed) { |
| 130 | tpm_sync(); |
| 131 | /* |
| 132 | * During the first invocation of this function on each stage |
| 133 | * this if () clause code does not run (as tpm_sync_needed |
| 134 | * value is zero), during all following invocations the |
| 135 | * stopwatch below is guaranteed to be started. |
| 136 | */ |
| 137 | if (!stopwatch_expired(&wake_up_sw)) |
| 138 | wakeup_needed = 0; |
| 139 | } else { |
| 140 | tpm_sync_needed = 1; |
| 141 | } |
Vadim Bendebury | 3b62d6b | 2017-10-30 18:29:03 -0700 | [diff] [blame] | 142 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 143 | if (wakeup_needed) { |
| 144 | /* Just in case Cr50 is asleep. */ |
| 145 | spi_claim_bus(&spi_slave); |
| 146 | udelay(1); |
| 147 | spi_release_bus(&spi_slave); |
| 148 | udelay(100); |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * The Cr50 on H1 does not go to sleep for 1 second after any |
| 153 | * SPI slave activity, let's be conservative and limit the |
| 154 | * window to 900 ms. |
| 155 | */ |
| 156 | stopwatch_init_msecs_expire(&wake_up_sw, 900); |
| 157 | } |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 158 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 159 | /* |
| 160 | * The first byte of the frame header encodes the transaction type |
| 161 | * (read or write) and transfer size (set to lentgh - 1), limited to |
| 162 | * 64 bytes. |
| 163 | */ |
| 164 | header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); |
| 165 | |
| 166 | /* The rest of the frame header is the TPM register address. */ |
| 167 | for (i = 0; i < 3; i++) |
| 168 | header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; |
| 169 | |
| 170 | /* CS assert wakes up the slave. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 171 | spi_claim_bus(&spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 172 | |
| 173 | /* |
| 174 | * The TCG TPM over SPI specification introduces the notion of SPI |
| 175 | * flow control (Section "6.4.5 Flow Control"). |
| 176 | * |
| 177 | * Again, the slave (TPM device) expects each transaction to start |
| 178 | * with a 4 byte header trasmitted by master. The header indicates if |
| 179 | * the master needs to read or write a register, and the register |
| 180 | * address. |
| 181 | * |
| 182 | * If the slave needs to stall the transaction (for instance it is not |
| 183 | * ready to send the register value to the master), it sets the MOSI |
| 184 | * line to 0 during the last clock of the 4 byte header. In this case |
| 185 | * the master is supposed to start polling the SPI bus, one byte at |
| 186 | * time, until the last bit in the received byte (transferred during |
| 187 | * the last clock of the byte) is set to 1. |
| 188 | * |
| 189 | * Due to some SPI controllers' shortcomings (Rockchip comes to |
| 190 | * mind...) we trasmit the 4 byte header without checking the byte |
| 191 | * transmitted by the TPM during the transaction's last byte. |
| 192 | * |
| 193 | * We know that cr50 is guaranteed to set the flow control bit to 0 |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 194 | * during the header transfer. Real TPM2 are fast enough to not require |
| 195 | * to stall the master. They might still use this feature, so test the |
| 196 | * last bit after shifting in the address bytes. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 197 | * crosbug.com/p/52132 has been opened to track this. |
| 198 | */ |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 199 | |
| 200 | header_resp.body[3] = 0; |
| 201 | if (CONFIG(TPM_CR50)) |
| 202 | ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0); |
| 203 | else |
| 204 | ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), |
| 205 | header_resp.body, sizeof(header_resp.body)); |
| 206 | if (ret) { |
| 207 | printk(BIOS_ERR, "SPI-TPM: transfer error\n"); |
| 208 | spi_release_bus(&spi_slave); |
| 209 | return 0; |
| 210 | } |
| 211 | |
| 212 | if (header_resp.body[3] & 1) |
| 213 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 214 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 215 | /* |
| 216 | * Now poll the bus until TPM removes the stall bit. Give it up to 100 |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 217 | * ms to sort it out - it could be saving stuff in nvram at some point. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 218 | */ |
| 219 | stopwatch_init_msecs_expire(&sw, 100); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 220 | do { |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 221 | if (stopwatch_expired(&sw)) { |
| 222 | printk(BIOS_ERR, "TPM flow control failure\n"); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 223 | spi_release_bus(&spi_slave); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 224 | return 0; |
| 225 | } |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 226 | spi_xfer(&spi_slave, NULL, 0, &byte, 1); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 227 | } while (!(byte & 1)); |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 228 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 229 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | /* |
| 233 | * Print out the contents of a buffer, if debug is enabled. Skip registers |
| 234 | * other than FIFO, unless debug_level_ is 2. |
| 235 | */ |
| 236 | static void trace_dump(const char *prefix, uint32_t reg, |
| 237 | size_t bytes, const uint8_t *buffer, |
| 238 | int force) |
| 239 | { |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 240 | static char prev_prefix; |
| 241 | static unsigned int prev_reg; |
| 242 | static int current_char; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 243 | const int BYTES_PER_LINE = 32; |
| 244 | |
| 245 | if (!force) { |
| 246 | if (!debug_level_) |
| 247 | return; |
| 248 | |
| 249 | if ((debug_level_ < 2) && (reg != TPM_DATA_FIFO_REG)) |
| 250 | return; |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * Do not print register address again if the last dump print was for |
| 255 | * that register. |
| 256 | */ |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 257 | if (prev_prefix != *prefix || (prev_reg != reg)) { |
| 258 | prev_prefix = *prefix; |
| 259 | prev_reg = reg; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 260 | printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 261 | current_char = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { |
| 265 | /* |
| 266 | * This must be a regular register address, print the 32 bit |
| 267 | * value. |
| 268 | */ |
| 269 | printk(BIOS_DEBUG, " %8.8x", *(const uint32_t *)buffer); |
| 270 | } else { |
| 271 | int i; |
| 272 | |
| 273 | /* |
| 274 | * Data read from or written to FIFO or not in 4 byte |
| 275 | * quantiites is printed byte at a time. |
| 276 | */ |
| 277 | for (i = 0; i < bytes; i++) { |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 278 | if (current_char && |
| 279 | !(current_char % BYTES_PER_LINE)) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 280 | printk(BIOS_DEBUG, "\n "); |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 281 | current_char = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 282 | } |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 283 | (current_char)++; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 284 | printk(BIOS_DEBUG, " %2.2x", buffer[i]); |
| 285 | } |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | /* |
| 290 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 291 | * write the actual bytes to the register. |
| 292 | */ |
| 293 | static void write_bytes(const void *buffer, size_t bytes) |
| 294 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 295 | spi_xfer(&spi_slave, buffer, bytes, NULL, 0); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 296 | } |
| 297 | |
| 298 | /* |
| 299 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 300 | * read the actual bytes from the register. |
| 301 | */ |
| 302 | static void read_bytes(void *buffer, size_t bytes) |
| 303 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 304 | spi_xfer(&spi_slave, NULL, 0, buffer, bytes); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | /* |
| 308 | * To write a register, start transaction, transfer data to the TPM, deassert |
| 309 | * CS when done. |
| 310 | * |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 311 | * Returns one to indicate success, zero to indicate failure. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 312 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 313 | static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t bytes) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 314 | { |
| 315 | trace_dump("W", reg_number, bytes, buffer, 0); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 316 | if (!start_transaction(false, bytes, reg_number)) |
| 317 | return 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 318 | write_bytes(buffer, bytes); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 319 | spi_release_bus(&spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 320 | return 1; |
| 321 | } |
| 322 | |
| 323 | /* |
| 324 | * To read a register, start transaction, transfer data from the TPM, deassert |
| 325 | * CS when done. |
| 326 | * |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 327 | * Returns one to indicate success, zero to indicate failure. In case of |
| 328 | * failure zero out the user buffer. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 329 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 330 | static int tpm2_read_reg(unsigned int reg_number, void *buffer, size_t bytes) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 331 | { |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 332 | if (!start_transaction(true, bytes, reg_number)) { |
| 333 | memset(buffer, 0, bytes); |
| 334 | return 0; |
| 335 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 336 | read_bytes(buffer, bytes); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 337 | spi_release_bus(&spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 338 | trace_dump("R", reg_number, bytes, buffer, 0); |
| 339 | return 1; |
| 340 | } |
| 341 | |
| 342 | /* |
| 343 | * Status register is accessed often, wrap reading and writing it into |
| 344 | * dedicated functions. |
| 345 | */ |
| 346 | static int read_tpm_sts(uint32_t *status) |
| 347 | { |
| 348 | return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); |
| 349 | } |
| 350 | |
| 351 | static int write_tpm_sts(uint32_t status) |
| 352 | { |
| 353 | return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); |
| 354 | } |
| 355 | |
| 356 | /* |
| 357 | * The TPM may limit the transaction bytes count (burst count) below the 64 |
| 358 | * bytes max. The current value is available as a field of the status |
| 359 | * register. |
| 360 | */ |
| 361 | static uint32_t get_burst_count(void) |
| 362 | { |
| 363 | uint32_t status; |
| 364 | |
| 365 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 366 | return (status & TPM_STS_BURST_COUNT_MASK) >> TPM_STS_BURST_COUNT_SHIFT; |
| 367 | } |
| 368 | |
| 369 | static uint8_t tpm2_read_access_reg(void) |
| 370 | { |
| 371 | uint8_t access; |
| 372 | tpm2_read_reg(TPM_ACCESS_REG, &access, sizeof(access)); |
| 373 | /* We do not care about access establishment bit state. Ignore it. */ |
| 374 | return access & ~TPM_ACCESS_ESTABLISHMENT; |
| 375 | } |
| 376 | |
| 377 | static void tpm2_write_access_reg(uint8_t cmd) |
| 378 | { |
| 379 | /* Writes to access register can set only 1 bit at a time. */ |
| 380 | assert (!(cmd & (cmd - 1))); |
| 381 | |
| 382 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 383 | } |
| 384 | |
| 385 | static int tpm2_claim_locality(void) |
| 386 | { |
| 387 | uint8_t access; |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 388 | struct stopwatch sw; |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 389 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 390 | /* |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 391 | * Locality is released by TPM reset. |
| 392 | * |
| 393 | * If locality is taken at this point, this could be due to the fact |
| 394 | * that the TPM is performing a long operation and has not processed |
| 395 | * reset request yet. We'll wait up to CR50_TIMEOUT_INIT_MS and see if |
| 396 | * it releases locality when reset is processed. |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 397 | */ |
| 398 | stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_INIT_MS); |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 399 | do { |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 400 | access = tpm2_read_access_reg(); |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 401 | if (access & TPM_ACCESS_ACTIVE_LOCALITY) { |
| 402 | /* |
| 403 | * Don't bombard the chip with traffic, let it keep |
| 404 | * processing the command. |
| 405 | */ |
| 406 | mdelay(2); |
| 407 | continue; |
| 408 | } |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 409 | |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 410 | /* |
| 411 | * Ok, the locality is free, TPM must be reset, let's claim |
| 412 | * it. |
| 413 | */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 414 | |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 415 | tpm2_write_access_reg(TPM_ACCESS_REQUEST_USE); |
| 416 | access = tpm2_read_access_reg(); |
| 417 | if (access != (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) { |
| 418 | break; |
| 419 | } |
| 420 | |
| 421 | printk(BIOS_INFO, "TPM ready after %ld ms\n", |
| 422 | stopwatch_duration_msecs(&sw)); |
| 423 | |
| 424 | return 1; |
| 425 | } while (!stopwatch_expired(&sw)); |
| 426 | |
| 427 | printk(BIOS_ERR, |
| 428 | "Failed to claim locality 0 after %ld ms, status: %#x\n", |
| 429 | stopwatch_duration_msecs(&sw), access); |
| 430 | |
| 431 | return 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 432 | } |
| 433 | |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 434 | static int cr50_parse_fw_version(const char *version_str, struct cr50_firmware_version *ver) |
| 435 | { |
| 436 | int epoch, major, minor; |
| 437 | |
| 438 | char *number = strstr(version_str, " RW_A:"); |
| 439 | if (!number) |
| 440 | number = strstr(version_str, " RW_B:"); |
| 441 | if (!number) |
| 442 | return -1; |
| 443 | number += 6; /* Skip past the colon. */ |
| 444 | |
| 445 | epoch = skip_atoi(&number); |
| 446 | if (*number++ != '.') |
| 447 | return -2; |
| 448 | major = skip_atoi(&number); |
| 449 | if (*number++ != '.') |
| 450 | return -2; |
| 451 | minor = skip_atoi(&number); |
| 452 | |
| 453 | ver->epoch = epoch; |
| 454 | ver->major = major; |
| 455 | ver->minor = minor; |
| 456 | return 0; |
| 457 | } |
| 458 | |
| 459 | static int cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) |
| 460 | { |
| 461 | /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 |
| 462 | * and onwards. */ |
| 463 | if (version->epoch > 0 || version->major >= 7 |
| 464 | || (version->major >= 5 && version->minor >= 5)) |
| 465 | return 1; |
| 466 | printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", |
| 467 | version->epoch, version->major, version->minor); |
| 468 | return 0; |
| 469 | } |
| 470 | |
| 471 | /** |
| 472 | * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. |
| 473 | */ |
| 474 | static void cr50_set_board_cfg(void) |
| 475 | { |
| 476 | uint32_t board_cfg_value; |
| 477 | if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) |
| 478 | return; |
| 479 | /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ |
| 480 | if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { |
| 481 | printk(BIOS_INFO, "Error reading from cr50\n"); |
| 482 | return; |
| 483 | } |
| 484 | if ((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { |
| 485 | printk(BIOS_INFO, |
| 486 | "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", |
| 487 | board_cfg_value, CR50_BOARD_CFG_VALUE); |
| 488 | return; |
| 489 | } |
| 490 | if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) { |
| 491 | /* The high bit is set, meaning that the Cr50 is already locked on a particular |
| 492 | * value for the register, but not the one we wanted. */ |
| 493 | printk(BIOS_ERR, |
| 494 | "ERROR: Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", |
| 495 | board_cfg_value, CR50_BOARD_CFG_VALUE); |
| 496 | return; |
| 497 | } |
| 498 | printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", |
| 499 | board_cfg_value, CR50_BOARD_CFG_VALUE); |
| 500 | board_cfg_value = CR50_BOARD_CFG_VALUE; |
| 501 | if (!tpm2_write_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) |
| 502 | printk(BIOS_INFO, "Error writing to cr50\n"); |
| 503 | } |
| 504 | |
| 505 | /* |
| 506 | * Expose method to read the CR50_BOARD_CFG register, will return zero if |
| 507 | * register not supported by Cr50 firmware. |
| 508 | */ |
| 509 | static uint32_t cr50_get_board_cfg(void) |
| 510 | { |
| 511 | uint32_t board_cfg_value; |
| 512 | if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) |
| 513 | return 0; |
| 514 | if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { |
| 515 | printk(BIOS_INFO, "Error reading from cr50\n"); |
| 516 | return 0; |
| 517 | } |
| 518 | return board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK; |
| 519 | } |
| 520 | |
| 521 | bool cr50_is_long_interrupt_pulse_enabled(void) |
| 522 | { |
| 523 | return cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE; |
| 524 | } |
| 525 | |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 526 | /* Device/vendor ID values of the TPM devices this driver supports. */ |
| 527 | static const uint32_t supported_did_vids[] = { |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 528 | 0x00281ae0, /* H1 based Cr50 security chip. */ |
| 529 | 0x0000104a /* ST33HTPH2E32 */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 530 | }; |
| 531 | |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 532 | static int first_access_this_boot(void) |
| 533 | { |
| 534 | return ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT); |
| 535 | } |
| 536 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 537 | int tpm2_init(struct spi_slave *spi_if) |
| 538 | { |
| 539 | uint32_t did_vid, status; |
| 540 | uint8_t cmd; |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 541 | int retries; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 542 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 543 | memcpy(&spi_slave, spi_if, sizeof(*spi_if)); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 544 | |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 545 | /* clear any pending IRQs */ |
Shelley Chen | f2e7b37 | 2017-12-15 15:25:08 -0800 | [diff] [blame] | 546 | tis_plat_irq_status(); |
| 547 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 548 | /* |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 549 | * 150 ms should be enough to synchronize with the TPM even under the |
| 550 | * worst nested reset request conditions. In vast majority of cases |
| 551 | * there would be no wait at all. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 552 | */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 553 | printk(BIOS_INFO, "Probing TPM: "); |
| 554 | for (retries = 15; retries > 0; retries--) { |
| 555 | int i; |
| 556 | |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 557 | /* In case of failure to read div_vid is set to zero. */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 558 | tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); |
| 559 | |
| 560 | for (i = 0; i < ARRAY_SIZE(supported_did_vids); i++) |
| 561 | if (did_vid == supported_did_vids[i]) |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 562 | break; /* TPM is up and ready. */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 563 | |
| 564 | if (i < ARRAY_SIZE(supported_did_vids)) |
| 565 | break; |
| 566 | |
| 567 | /* TPM might be resetting, let's retry in a bit. */ |
| 568 | mdelay(10); |
| 569 | printk(BIOS_INFO, "."); |
| 570 | } |
| 571 | |
| 572 | if (!retries) { |
| 573 | printk(BIOS_ERR, "\n%s: Failed to connect to the TPM\n", |
| 574 | __func__); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 575 | return -1; |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 576 | } |
| 577 | |
| 578 | printk(BIOS_INFO, " done!\n"); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 579 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 580 | // FIXME: Move this to tpm_setup() |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 581 | if (first_access_this_boot()) |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 582 | /* |
| 583 | * Claim locality 0, do it only during the first |
| 584 | * initialization after reset. |
| 585 | */ |
| 586 | if (!tpm2_claim_locality()) |
| 587 | return -1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 588 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 589 | if (!read_tpm_sts(&status)) { |
| 590 | printk(BIOS_ERR, "Reading status reg failed\n"); |
| 591 | return -1; |
| 592 | } |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 593 | if ((status & TPM_STS_FAMILY_MASK) != TPM_STS_FAMILY_TPM_2_0) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 594 | printk(BIOS_ERR, "unexpected TPM family value, status: %#x\n", |
| 595 | status); |
| 596 | return -1; |
| 597 | } |
| 598 | |
| 599 | /* |
| 600 | * Locality claimed, read the revision value and set up the tpm_info |
| 601 | * structure. |
| 602 | */ |
| 603 | tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 604 | tpm_info.vendor_id = did_vid & 0xffff; |
| 605 | tpm_info.device_id = did_vid >> 16; |
| 606 | tpm_info.revision = cmd; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 607 | |
| 608 | printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 609 | tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 610 | |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 611 | /* Let's report device FW version if available. */ |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 612 | if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x1ae0) { |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 613 | int chunk_count = 0; |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 614 | size_t chunk_size = 50; |
| 615 | char version_str[301]; |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 616 | |
| 617 | /* |
| 618 | * Does not really matter what's written, this just makes sure |
| 619 | * the version is reported from the beginning. |
| 620 | */ |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 621 | tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 622 | |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 623 | /* |
| 624 | * Read chunk_size bytes at a time, last chunk will be zero padded. |
| 625 | */ |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 626 | do { |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 627 | tpm2_read_reg(TPM_FW_VER, |
| 628 | version_str + chunk_count * chunk_size, |
| 629 | chunk_size); |
| 630 | if (!version_str[++chunk_count * chunk_size - 1]) |
| 631 | /* Zero padding detected: end of string. */ |
| 632 | break; |
| 633 | /* Check if there is enough room for reading one more chunk. */ |
| 634 | } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); |
| 635 | version_str[chunk_count * chunk_size] = '\0'; |
| 636 | printk(BIOS_INFO, "Firmware version: %s\n", version_str); |
| 637 | if (cr50_parse_fw_version(version_str, &cr50_firmware_version)) { |
| 638 | printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); |
| 639 | return -1; |
| 640 | } |
| 641 | if (CR50_BOARD_CFG_VALUE) { |
| 642 | if (first_access_this_boot()) |
| 643 | cr50_set_board_cfg(); |
| 644 | } |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 645 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 646 | return 0; |
| 647 | } |
| 648 | |
| 649 | /* |
| 650 | * This is in seconds, certain TPM commands, like key generation, can take |
| 651 | * long time to complete. |
| 652 | * |
| 653 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 654 | * failure. |
| 655 | */ |
| 656 | #define MAX_STATUS_TIMEOUT 120 |
| 657 | static int wait_for_status(uint32_t status_mask, uint32_t status_expected) |
| 658 | { |
| 659 | uint32_t status; |
| 660 | struct stopwatch sw; |
| 661 | |
| 662 | stopwatch_init_usecs_expire(&sw, MAX_STATUS_TIMEOUT * 1000 * 1000); |
| 663 | do { |
| 664 | udelay(1000); |
| 665 | if (stopwatch_expired(&sw)) { |
| 666 | printk(BIOS_ERR, "failed to get expected status %x\n", |
| 667 | status_expected); |
| 668 | return false; |
| 669 | } |
| 670 | read_tpm_sts(&status); |
| 671 | } while ((status & status_mask) != status_expected); |
| 672 | |
| 673 | return 1; |
| 674 | } |
| 675 | |
| 676 | enum fifo_transfer_direction { |
| 677 | fifo_transmit = 0, |
| 678 | fifo_receive = 1 |
| 679 | }; |
| 680 | |
| 681 | /* Union allows to avoid casting away 'const' on transmit buffers. */ |
| 682 | union fifo_transfer_buffer { |
| 683 | uint8_t *rx_buffer; |
| 684 | const uint8_t *tx_buffer; |
| 685 | }; |
| 686 | |
| 687 | /* |
| 688 | * Transfer requested number of bytes to or from TPM FIFO, accounting for the |
| 689 | * current burst count value. |
| 690 | */ |
| 691 | static void fifo_transfer(size_t transfer_size, |
| 692 | union fifo_transfer_buffer buffer, |
| 693 | enum fifo_transfer_direction direction) |
| 694 | { |
| 695 | size_t transaction_size; |
| 696 | size_t burst_count; |
| 697 | size_t handled_so_far = 0; |
| 698 | |
| 699 | do { |
| 700 | do { |
| 701 | /* Could be zero when TPM is busy. */ |
| 702 | burst_count = get_burst_count(); |
| 703 | } while (!burst_count); |
| 704 | |
| 705 | transaction_size = transfer_size - handled_so_far; |
| 706 | transaction_size = MIN(transaction_size, burst_count); |
| 707 | |
| 708 | /* |
| 709 | * The SPI frame header does not allow to pass more than 64 |
| 710 | * bytes. |
| 711 | */ |
| 712 | transaction_size = MIN(transaction_size, 64); |
| 713 | |
| 714 | if (direction == fifo_receive) |
| 715 | tpm2_read_reg(TPM_DATA_FIFO_REG, |
| 716 | buffer.rx_buffer + handled_so_far, |
| 717 | transaction_size); |
| 718 | else |
| 719 | tpm2_write_reg(TPM_DATA_FIFO_REG, |
| 720 | buffer.tx_buffer + handled_so_far, |
| 721 | transaction_size); |
| 722 | |
| 723 | handled_so_far += transaction_size; |
| 724 | |
| 725 | } while (handled_so_far != transfer_size); |
| 726 | } |
| 727 | |
| 728 | size_t tpm2_process_command(const void *tpm2_command, size_t command_size, |
| 729 | void *tpm2_response, size_t max_response) |
| 730 | { |
| 731 | uint32_t status; |
| 732 | uint32_t expected_status_bits; |
| 733 | size_t payload_size; |
| 734 | size_t bytes_to_go; |
| 735 | const uint8_t *cmd_body = tpm2_command; |
| 736 | uint8_t *rsp_body = tpm2_response; |
| 737 | union fifo_transfer_buffer fifo_buffer; |
| 738 | const int HEADER_SIZE = 6; |
| 739 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 740 | /* Do not try using an uninitialized TPM. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 741 | if (!tpm_info.vendor_id) |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 742 | return 0; |
| 743 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 744 | /* Skip the two byte tag, read the size field. */ |
| 745 | payload_size = read_be32(cmd_body + 2); |
| 746 | |
| 747 | /* Sanity check. */ |
| 748 | if (payload_size != command_size) { |
| 749 | printk(BIOS_ERR, |
| 750 | "Command size mismatch: encoded %zd != requested %zd\n", |
| 751 | payload_size, command_size); |
| 752 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 753 | printk(BIOS_DEBUG, "\n"); |
| 754 | return 0; |
| 755 | } |
| 756 | |
| 757 | /* Let the TPM know that the command is coming. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 758 | write_tpm_sts(TPM_STS_COMMAND_READY); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 759 | |
| 760 | /* |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 761 | * TPM commands and responses written to and read from the FIFO |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 762 | * register (0x24) are datagrams of variable size, prepended by a 6 |
| 763 | * byte header. |
| 764 | * |
| 765 | * The specification description of the state machine is a bit vague, |
| 766 | * but from experience it looks like there is no need to wait for the |
| 767 | * sts.expect bit to be set, at least with the 9670 and cr50 devices. |
| 768 | * Just write the command into FIFO, making sure not to exceed the |
| 769 | * burst count or the maximum PDU size, whatever is smaller. |
| 770 | */ |
| 771 | fifo_buffer.tx_buffer = cmd_body; |
| 772 | fifo_transfer(command_size, fifo_buffer, fifo_transmit); |
| 773 | |
| 774 | /* Now tell the TPM it can start processing the command. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 775 | write_tpm_sts(TPM_STS_GO); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 776 | |
| 777 | /* Now wait for it to report that the response is ready. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 778 | expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 779 | if (!wait_for_status(expected_status_bits, expected_status_bits)) { |
| 780 | /* |
| 781 | * If timed out, which should never happen, let's at least |
| 782 | * print out the offending command. |
| 783 | */ |
| 784 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 785 | printk(BIOS_DEBUG, "\n"); |
| 786 | return 0; |
| 787 | } |
| 788 | |
| 789 | /* |
| 790 | * The response is ready, let's read it. First we read the FIFO |
| 791 | * payload header, to see how much data to expect. The response header |
| 792 | * size is fixed to six bytes, the total payload size is stored in |
| 793 | * network order in the last four bytes. |
| 794 | */ |
| 795 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body, HEADER_SIZE); |
| 796 | |
| 797 | /* Find out the total payload size, skipping the two byte tag. */ |
| 798 | payload_size = read_be32(rsp_body + 2); |
| 799 | |
| 800 | if (payload_size > max_response) { |
| 801 | /* |
| 802 | * TODO(vbendeb): at least drain the FIFO here or somehow let |
| 803 | * the TPM know that the response can be dropped. |
| 804 | */ |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 805 | printk(BIOS_ERR, " TPM response too long (%zd bytes)", |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 806 | payload_size); |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | /* |
| 811 | * Now let's read all but the last byte in the FIFO to make sure the |
| 812 | * status register is showing correct flow control bits: 'more data' |
| 813 | * until the last byte and then 'no more data' once the last byte is |
| 814 | * read. |
| 815 | */ |
| 816 | bytes_to_go = payload_size - 1 - HEADER_SIZE; |
| 817 | fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; |
| 818 | fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive); |
| 819 | |
| 820 | /* Verify that there is still data to read. */ |
| 821 | read_tpm_sts(&status); |
| 822 | if ((status & expected_status_bits) != expected_status_bits) { |
| 823 | printk(BIOS_ERR, "unexpected intermediate status %#x\n", |
| 824 | status); |
| 825 | return 0; |
| 826 | } |
| 827 | |
| 828 | /* Read the last byte of the PDU. */ |
| 829 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body + payload_size - 1, 1); |
| 830 | |
| 831 | /* Terminate the dump, if enabled. */ |
| 832 | if (debug_level_) |
| 833 | printk(BIOS_DEBUG, "\n"); |
| 834 | |
| 835 | /* Verify that 'data available' is not asseretd any more. */ |
| 836 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 837 | if ((status & expected_status_bits) != TPM_STS_VALID) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 838 | printk(BIOS_ERR, "unexpected final status %#x\n", status); |
| 839 | return 0; |
| 840 | } |
| 841 | |
| 842 | /* Move the TPM back to idle state. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 843 | write_tpm_sts(TPM_STS_COMMAND_READY); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 844 | |
| 845 | return payload_size; |
| 846 | } |
Karthikeyan Ramasubramanian | 7b58f94 | 2020-08-20 22:53:00 -0600 | [diff] [blame^] | 847 | |
| 848 | void cr50_get_firmware_version(struct cr50_firmware_version *version) |
| 849 | { |
| 850 | memcpy(version, &cr50_firmware_version, sizeof(*version)); |
| 851 | } |