Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lee Leahy | 47bd2d9 | 2016-07-24 18:12:16 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015-2016 Intel Corp. |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 5 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
Philipp Deppenwiese | c07f8fb | 2018-02-27 19:40:52 +0100 | [diff] [blame] | 14 | #include <security/vboot/antirollback.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 15 | #include <arch/symbols.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 16 | #include <assert.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 17 | #include <cbfs.h> |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 18 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 19 | #include <cf9_reset.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 20 | #include <console/console.h> |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 21 | #include <elog.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 22 | #include <fsp/api.h> |
| 23 | #include <fsp/util.h> |
| 24 | #include <memrange.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 25 | #include <mrc_cache.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 26 | #include <program_loading.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 27 | #include <romstage_handoff.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 28 | #include <string.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 29 | #include <symbols.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 30 | #include <timestamp.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 31 | #include <security/vboot/vboot_common.h> |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 32 | #include <security/tpm/tspi.h> |
Furquan Shaikh | 2db5bac | 2016-11-07 23:57:48 -0800 | [diff] [blame] | 33 | #include <vb2_api.h> |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 34 | #include <fsp/memory_init.h> |
Elyes HAOUAS | bd1683d | 2019-05-15 21:05:37 +0200 | [diff] [blame] | 35 | #include <types.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 36 | |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 37 | static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); |
| 38 | |
Joel Kitching | 2c8243c | 2019-03-11 17:47:24 +0800 | [diff] [blame] | 39 | /* TPM MRC hash functionality depends on vboot starting before memory init. */ |
| 40 | _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || |
| 41 | CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), |
| 42 | "for TPM MRC hash functionality, vboot must start in bootblock"); |
| 43 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 44 | static void save_memory_training_data(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 45 | { |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 46 | size_t mrc_data_size; |
| 47 | const void *mrc_data; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 48 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 49 | if (!CONFIG(CACHE_MRC_SETTINGS) || s3wake) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 50 | return; |
| 51 | |
| 52 | mrc_data = fsp_find_nv_storage_data(&mrc_data_size); |
| 53 | if (!mrc_data) { |
| 54 | printk(BIOS_ERR, "Couldn't find memory training data HOB.\n"); |
| 55 | return; |
| 56 | } |
| 57 | |
| 58 | /* |
| 59 | * Save MRC Data to CBMEM. By always saving the data this forces |
| 60 | * a retrain after a trip through Chrome OS recovery path. The |
| 61 | * code which saves the data to flash doesn't write if the latest |
| 62 | * training data matches this one. |
| 63 | */ |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 64 | if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, |
| 65 | mrc_data_size) < 0) |
| 66 | printk(BIOS_ERR, "Failed to stash MRC data\n"); |
Furquan Shaikh | 2db5bac | 2016-11-07 23:57:48 -0800 | [diff] [blame] | 67 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 68 | if (CONFIG(FSP2_0_USES_TPM_MRC_HASH)) |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 69 | mrc_cache_update_hash(mrc_data, mrc_data_size); |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 70 | } |
| 71 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 72 | static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 73 | { |
| 74 | struct range_entry fsp_mem; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 75 | |
Lee Leahy | 52d0c68 | 2016-08-01 15:47:42 -0700 | [diff] [blame] | 76 | if (fsp_find_reserved_memory(&fsp_mem)) |
| 77 | die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 78 | |
| 79 | /* initialize cbmem by adding FSP reserved memory first thing */ |
| 80 | if (!s3wake) { |
| 81 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 82 | range_entry_size(&fsp_mem)); |
| 83 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 84 | range_entry_size(&fsp_mem))) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 85 | if (CONFIG(HAVE_ACPI_RESUME)) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 86 | printk(BIOS_ERR, |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 87 | "Failed to recover CBMEM in S3 resume.\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 88 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 89 | /* FIXME: A "system" reset is likely enough: */ |
| 90 | full_reset(); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 91 | } |
| 92 | } |
| 93 | |
| 94 | /* make sure FSP memory is reserved in cbmem */ |
| 95 | if (range_entry_base(&fsp_mem) != |
| 96 | (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 97 | die("Failed to accommodate FSP reserved memory request!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 98 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 99 | save_memory_training_data(s3wake, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 100 | |
| 101 | /* Create romstage handof information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 102 | romstage_handoff_init(s3wake); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 103 | } |
| 104 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 105 | static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 106 | { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 107 | struct region_device rdev; |
| 108 | void *data; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 109 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 110 | arch_upd->NvsBufferPtr = NULL; |
| 111 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 112 | if (!CONFIG(CACHE_MRC_SETTINGS)) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 113 | return; |
| 114 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 115 | /* |
| 116 | * In recovery mode, force retraining: |
| 117 | * 1. Recovery cache is not supported, or |
| 118 | * 2. Memory retrain switch is set. |
| 119 | */ |
| 120 | if (vboot_recovery_mode_enabled()) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 121 | if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 122 | return; |
| 123 | if (vboot_recovery_mode_memory_retrain()) |
| 124 | return; |
| 125 | } |
Aaron Durbin | 98ea636 | 2016-07-18 11:31:53 -0500 | [diff] [blame] | 126 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 127 | if (mrc_cache_get_current(MRC_TRAINING_DATA, fsp_version, &rdev) < 0) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 128 | return; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 129 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 130 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 131 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 132 | data = rdev_mmap_full(&rdev); |
| 133 | |
| 134 | if (data == NULL) |
| 135 | return; |
| 136 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 137 | if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 138 | !mrc_cache_verify_hash(data, region_device_sz(&rdev))) |
Furquan Shaikh | 2db5bac | 2016-11-07 23:57:48 -0800 | [diff] [blame] | 139 | return; |
| 140 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 141 | /* MRC cache found */ |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 142 | arch_upd->NvsBufferPtr = data; |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 143 | |
| 144 | printk(BIOS_SPEW, "MRC cache found, size %zx\n", |
| 145 | region_device_sz(&rdev)); |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 146 | } |
| 147 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 148 | static enum cb_err check_region_overlap(const struct memranges *ranges, |
| 149 | const char *description, |
| 150 | uintptr_t begin, uintptr_t end) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 151 | { |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 152 | const struct range_entry *r; |
| 153 | |
| 154 | memranges_each_entry(r, ranges) { |
| 155 | if (end <= range_entry_base(r)) |
| 156 | continue; |
| 157 | if (begin >= range_entry_end(r)) |
| 158 | continue; |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 159 | printk(BIOS_CRIT, "'%s' overlaps currently running program: " |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 160 | "[%p, %p)\n", description, (void *)begin, (void *)end); |
| 161 | return CB_ERR; |
| 162 | } |
| 163 | |
| 164 | return CB_SUCCESS; |
| 165 | } |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 166 | |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 167 | static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, |
| 168 | const struct memranges *memmap) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 169 | { |
| 170 | uintptr_t stack_begin; |
| 171 | uintptr_t stack_end; |
| 172 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 173 | /* |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 174 | * FSPM_UPD passed here is populated with default values |
| 175 | * provided by the blob itself. We let FSPM use top of CAR |
| 176 | * region of the size it requests. |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 177 | */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 178 | stack_end = (uintptr_t)_car_region_end; |
| 179 | stack_begin = stack_end - arch_upd->StackSize; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 180 | if (check_region_overlap(memmap, "FSPM stack", stack_begin, |
| 181 | stack_end) != CB_SUCCESS) |
| 182 | return CB_ERR; |
| 183 | |
| 184 | arch_upd->StackBase = (void *)stack_begin; |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 185 | return CB_SUCCESS; |
| 186 | } |
| 187 | |
| 188 | static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, |
| 189 | bool s3wake, uint32_t fsp_version, |
| 190 | const struct memranges *memmap) |
| 191 | { |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 192 | /* |
| 193 | * FSP 2.1 version would use same stack as coreboot instead of |
| 194 | * setting up separate stack frame. FSP 2.1 would not relocate stack |
| 195 | * top and does not reinitialize stack pointer. The parameters passed |
| 196 | * as StackBase and StackSize are actually for temporary RAM and HOBs |
| 197 | * and are not related to FSP stack at all. |
| 198 | */ |
| 199 | if (CONFIG(FSP_USES_CB_STACK)) { |
| 200 | arch_upd->StackBase = temp_ram; |
| 201 | arch_upd->StackSize = sizeof(temp_ram); |
| 202 | } else if (setup_fsp_stack_frame(arch_upd, memmap)) { |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 203 | return CB_ERR; |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 204 | } |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 205 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 206 | fsp_fill_mrc_cache(arch_upd, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 207 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 208 | /* Configure bootmode */ |
| 209 | if (s3wake) { |
| 210 | /* |
| 211 | * For S3 resume case, if valid mrc cache data is not found or |
| 212 | * RECOVERY_MRC_CACHE hash verification fails, the S3 data |
| 213 | * pointer would be null and S3 resume fails with fsp-m |
| 214 | * returning error. Invoking a reset here saves time. |
| 215 | */ |
| 216 | if (!arch_upd->NvsBufferPtr) |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 217 | /* FIXME: A "system" reset is likely enough: */ |
| 218 | full_reset(); |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 219 | arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME; |
| 220 | } else { |
| 221 | if (arch_upd->NvsBufferPtr) |
| 222 | arch_upd->BootMode = |
| 223 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 224 | else |
| 225 | arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 226 | } |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 227 | |
Marshall Dawson | 22d66ef | 2019-08-30 14:52:37 -0600 | [diff] [blame^] | 228 | printk(BIOS_SPEW, "bootmode is set to: %d\n", arch_upd->BootMode); |
Aamir Bohra | 276c06a | 2017-12-26 17:54:45 +0530 | [diff] [blame] | 229 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 230 | return CB_SUCCESS; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 231 | } |
| 232 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 233 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 234 | uint8_t fsp_memory_mainboard_version(void) |
| 235 | { |
| 236 | return 0; |
| 237 | } |
| 238 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 239 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 240 | uint8_t fsp_memory_soc_version(void) |
| 241 | { |
| 242 | return 0; |
| 243 | } |
| 244 | |
| 245 | /* |
| 246 | * Allow SoC and/or mainboard to bump the revision of the FSP setting |
| 247 | * number. The FSP spec uses the low 8 bits as the build number. Take over |
| 248 | * bits 3:0 for the SoC setting and bits 7:4 for the mainboard. That way |
| 249 | * a tweak in the settings will bump the version used to track the cached |
| 250 | * setting which triggers retraining when the FSP version hasn't changed, but |
| 251 | * the SoC or mainboard settings have. |
| 252 | */ |
| 253 | static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) |
| 254 | { |
| 255 | /* Use the full FSP version by default. */ |
| 256 | uint32_t ver = hdr->fsp_revision; |
| 257 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 258 | if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 259 | return ver; |
| 260 | |
| 261 | ver &= ~0xff; |
| 262 | ver |= (0xf & fsp_memory_mainboard_version()) << 4; |
| 263 | ver |= (0xf & fsp_memory_soc_version()) << 0; |
| 264 | |
| 265 | return ver; |
| 266 | } |
| 267 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 268 | static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 269 | const struct memranges *memmap) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 270 | { |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 271 | uint32_t status; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 272 | fsp_memory_init_fn fsp_raminit; |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 273 | FSPM_UPD fspm_upd, *upd; |
| 274 | FSPM_ARCH_UPD *arch_upd; |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 275 | uint32_t fsp_version; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 276 | |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 277 | post_code(POST_MEM_PREINIT_PREP_START); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 278 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 279 | fsp_version = fsp_memory_settings_version(hdr); |
| 280 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 281 | upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 282 | |
Lee Leahy | e686ee8 | 2017-03-10 08:45:30 -0800 | [diff] [blame] | 283 | if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 284 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 285 | "Invalid FSPM signature!\n"); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 286 | |
| 287 | /* Copy the default values from the UPD area */ |
| 288 | memcpy(&fspm_upd, upd, sizeof(fspm_upd)); |
| 289 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 290 | arch_upd = &fspm_upd.FspmArchUpd; |
| 291 | |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 292 | /* Reserve enough memory under TOLUD to save CBMEM header */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 293 | arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 294 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 295 | /* Fill common settings on behalf of chipset. */ |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 296 | if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 297 | memmap) != CB_SUCCESS) |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 298 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 299 | "FSPM_ARCH_UPD not found!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 300 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 301 | /* Give SoC and mainboard a chance to update the UPD */ |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 302 | platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 303 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 304 | if (CONFIG(MMA)) |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 305 | setup_mma(&fspm_upd.FspmConfig); |
| 306 | |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 307 | post_code(POST_MEM_PREINIT_PREP_END); |
| 308 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 309 | /* Call FspMemoryInit */ |
| 310 | fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 311 | fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 312 | |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 313 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 314 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 315 | status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); |
Subrata Banik | 0755ab9 | 2017-07-12 15:31:06 +0530 | [diff] [blame] | 316 | post_code(POST_FSP_MEMORY_EXIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 317 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 318 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 319 | /* Handle any errors returned by FspMemoryInit */ |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 320 | fsp_handle_reset(status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 321 | if (status != FSP_SUCCESS) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 322 | printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); |
Keith Short | 2430263 | 2019-05-16 14:08:31 -0600 | [diff] [blame] | 323 | die_with_post_code(POST_RAM_FAILURE, |
| 324 | "FspMemoryInit returned an error!\n"); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 325 | } |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 326 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 327 | do_fsp_post_memory_init(s3wake, fsp_version); |
Matthew Garrett | 78b58a4 | 2018-07-28 16:53:16 -0700 | [diff] [blame] | 328 | |
| 329 | /* |
| 330 | * fsp_debug_after_memory_init() checks whether the end of the tolum |
| 331 | * region is the same as the top of cbmem, so must be called here |
| 332 | * after cbmem has been initialised in do_fsp_post_memory_init(). |
| 333 | */ |
| 334 | fsp_debug_after_memory_init(status); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 335 | } |
| 336 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 337 | /* Load the binary into the memory specified by the info header. */ |
| 338 | static enum cb_err load_fspm_mem(struct fsp_header *hdr, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 339 | const struct region_device *rdev, |
| 340 | const struct memranges *memmap) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 341 | { |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 342 | uintptr_t fspm_begin; |
| 343 | uintptr_t fspm_end; |
| 344 | |
| 345 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 346 | return CB_ERR; |
| 347 | |
| 348 | fspm_begin = hdr->image_base; |
| 349 | fspm_end = fspm_begin + hdr->image_size; |
| 350 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 351 | if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != |
| 352 | CB_SUCCESS) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 353 | return CB_ERR; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 354 | |
| 355 | /* Load binary into memory at provided address. */ |
| 356 | if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0) |
| 357 | return CB_ERR; |
| 358 | |
| 359 | return CB_SUCCESS; |
| 360 | } |
| 361 | |
| 362 | /* Handle the case when FSPM is running XIP. */ |
| 363 | static enum cb_err load_fspm_xip(struct fsp_header *hdr, |
| 364 | const struct region_device *rdev) |
| 365 | { |
| 366 | void *base; |
| 367 | |
| 368 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 369 | return CB_ERR; |
| 370 | |
| 371 | base = rdev_mmap_full(rdev); |
| 372 | if ((uintptr_t)base != hdr->image_base) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 373 | printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 374 | (void *)(uintptr_t)hdr->image_base, base); |
| 375 | return CB_ERR; |
| 376 | } |
| 377 | |
| 378 | /* |
| 379 | * Since the component is XIP it's already in the address space. Thus, |
| 380 | * there's no need to rdev_munmap(). |
| 381 | */ |
| 382 | return CB_SUCCESS; |
| 383 | } |
| 384 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 385 | void fsp_memory_init(bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 386 | { |
| 387 | struct fsp_header hdr; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 388 | enum cb_err status; |
| 389 | struct cbfsf file_desc; |
| 390 | struct region_device file_data; |
| 391 | const char *name = CONFIG_FSP_M_CBFS; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 392 | struct memranges memmap; |
| 393 | struct range_entry freeranges[2]; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 394 | |
Kyösti Mälkki | 0889e93 | 2019-08-18 07:40:43 +0300 | [diff] [blame] | 395 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 396 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 397 | if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 398 | boot_count_increment(); |
| 399 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 400 | if (cbfs_boot_locate(&file_desc, name, NULL)) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 401 | printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 402 | die("FSPM not available!\n"); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | cbfs_file_data(&file_data, &file_desc); |
| 406 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 407 | /* Build up memory map of romstage address space including CAR. */ |
| 408 | memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); |
| 409 | memranges_insert(&memmap, (uintptr_t)_car_region_start, |
| 410 | _car_relocatable_data_end - _car_region_start, 0); |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 411 | memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 412 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 413 | if (!CONFIG(FSP_M_XIP)) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 414 | status = load_fspm_mem(&hdr, &file_data, &memmap); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 415 | else |
| 416 | status = load_fspm_xip(&hdr, &file_data); |
| 417 | |
Lee Leahy | e686ee8 | 2017-03-10 08:45:30 -0800 | [diff] [blame] | 418 | if (status != CB_SUCCESS) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 419 | die("Loading FSPM failed!\n"); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 420 | |
| 421 | /* Signal that FSP component has been loaded. */ |
| 422 | prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 423 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 424 | do_fsp_memory_init(&hdr, s3wake, &memmap); |
Kyösti Mälkki | 0889e93 | 2019-08-18 07:40:43 +0300 | [diff] [blame] | 425 | |
| 426 | timestamp_add_now(TS_AFTER_INITRAM); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 427 | } |