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review.coreboot.org / coreboot / 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 / . / src / southbridge / amd / cimx / sb800 / SBPLATFORM.h
blob: 760088632e3339a643f85edd6b174a48e3a9c38c [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]2
Elyes HAOUAS65fa5982014-07-22 23:12:38 +0200[diff] [blame]3#ifndef _AMD_SBPLATFORM_H_
4#define _AMD_SBPLATFORM_H_
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]5
Aaron Durbind907a342014-01-30 22:20:01 -0600[diff] [blame]6#include <stddef.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]7
8typedef unsigned long long PLACEHOLDER;
9
10#ifndef SBOEM_ACPI_RESTORE_SWSMI
11 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
12 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
13#endif
14
15#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
16
17/*
18/// Extended PCI Address
19typedef struct _EXT_PCI_ADDR {
20 UINT32 Reg :16; ///< / PCI Register
21 UINT32 Func:3; ///< / PCI Function
22 UINT32 Dev :5; ///< / PCI Device
23 UINT32 Bus :8; ///< / PCI Address
24} EXT_PCI_ADDR;
25
26/// PCI Address
27typedef union _PCI_ADDR {
28 UINT32 ADDR; ///< / 32 bit Address
29 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
30} PCI_ADDR;
31*/
32#endif
33#define FIXUP_PTR(ptr) ptr
34
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]35#if CONFIG(SB800_IMC_FWM)
Martin Rothe899e512012-12-05 16:07:11 -0700[diff] [blame]36 #define IMC_ENABLE_OVER_WRITE 0x01
37#endif
38
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]39#include "AmdSbLib.h"
40#include "Amd.h"
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +0200[diff] [blame]41#include <SB800.h>
42#include <SBTYPE.h>
43#include <ACPILIB.h>
44#include <SBDEF.h>
45#include <AMDSBLIB.h>
46#include <SBSUBFUN.h>
Elyes HAOUAS3b3d0852021-02-01 10:09:40 +0100[diff] [blame]47#include "platform_cfg.h"
48#include <OEM.h>
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +0200[diff] [blame]49#include <AMD.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]50
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]51//------------------------------------------------------------------------------------------------------------------------//
52/**
Martin Roth3c3a50c2014-12-16 20:50:26 -0700[diff] [blame]53 * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]54 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
55 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
56 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
57 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
58 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
59 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
60 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
61 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
62 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
63 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
64 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
65 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
66 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
67 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
68 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
69 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
70 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
Martin Roth3c3a50c2014-12-16 20:50:26 -0700[diff] [blame]71 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]72 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
73 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
74 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
75 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
76 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
77 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
78 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
79 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
80 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
81 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
82 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
83 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
84 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
85 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
86 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
87 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
88 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
89 */
90#define SB_CIMx_PARAMETER 0x02
91
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]92// Generic
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]93#define cimSpreadSpectrumDefault TRUE
94#define cimSpreadSpectrumTypeDefault 0x00 // Normal
95#define cimHpetTimerDefault TRUE
96#define cimHpetMsiDisDefault FALSE // Enable
97#define cimIrConfigDefault 0x00 // Disable
Scott Duplichane78ae242011-05-15 21:18:59 +0000[diff] [blame]98#define cimSpiFastReadEnableDefault 0x01 // Enable
99#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
Kerry She6209c822011-08-18 18:44:00 +0800[diff] [blame]100#define cimSioHwmPortEnableDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]101// GPP/AB Controller
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]102#define cimNbSbGen2Default TRUE
103#define cimAlinkPhyPllPowerDownDefault TRUE
104#define cimResetCpuOnSyncFloodDefault TRUE
105#define cimGppGen2Default FALSE
106#define cimGppMemWrImproveDefault TRUE
107#define cimGppPortAspmDefault FALSE
108#define cimGppLaneReversalDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]109#define cimGppPhyPllPowerDownDefault TRUE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]110// USB Controller
111#define cimUsbPhyPowerDownDefault FALSE
112// GEC Controller
113#define cimSBGecDebugBusDefault FALSE
114#define cimSBGecPwrDefault 0x03
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]115// Sata Controller
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]116#define cimSataSetMaxGen2Default 0x00
117#define cimSATARefClkSelDefault 0x10
118#define cimSATARefDivSelDefault 0x80
119#define cimSataAggrLinkPmCapDefault TRUE
120#define cimSataPortMultCapDefault TRUE
121#define cimSataPscCapDefault 0x00 // Enable
122#define cimSataSscCapDefault 0x00 // Enable
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]123#define cimSataFisBasedSwitchingDefault FALSE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]124#define cimSataCccSupportDefault FALSE
125#define cimSataClkAutoOffDefault FALSE
126#define cimNativepciesupportDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]127// Fusion Related
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]128#define cimAcDcMsgDefault FALSE
129#define cimTimerTickTrackDefault FALSE
130#define cimClockInterruptTagDefault FALSE
131#define cimOhciTrafficHandingDefault FALSE
132#define cimEhciTrafficHandingDefault FALSE
133#define cimFusionMsgCMultiCoreDefault FALSE
134#define cimFusionMsgCStageDefault FALSE
Stefan Reinauer971ebd82011-10-13 17:26:43 -0700[diff] [blame]135
136#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
Zheng Bao600784e2013-02-07 17:30:23 +0800[diff] [blame]137#include <spi-generic.h>
zbao01bd79f2012-03-23 11:36:08 +0800[diff] [blame]138
Elyes HAOUAS65fa5982014-07-22 23:12:38 +0200[diff] [blame]139#define BIOSRAM_INDEX 0xcd4
140#define BIOSRAM_DATA 0xcd5
zbao9bcdbf82012-04-05 13:18:49 +0800[diff] [blame]141
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]142#endif // _AMD_SBPLATFORM_H_