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review.coreboot.org / coreboot / 19f5ba81be265da3d1a2a15c106486677479dfd5 / . / src / southbridge / amd / cimx / sb800 / SBPLATFORM.h
blob: b356bf98e6d13148f873c03b4734ad411f41324b [file] [log] [blame]
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]1/*
2 *****************************************************************************
3 *
4 * This file is part of the coreboot project.
5 *
6 * Copyright (C) 2011 Advanced Micro Devices, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]16 * ***************************************************************************
17 *
18 */
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]19
Elyes HAOUAS65fa5982014-07-22 23:12:38 +0200[diff] [blame]20#ifndef _AMD_SBPLATFORM_H_
21#define _AMD_SBPLATFORM_H_
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]22
Aaron Durbind907a342014-01-30 22:20:01 -0600[diff] [blame]23#include <stddef.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]24
25typedef unsigned long long PLACEHOLDER;
26
27#ifndef SBOEM_ACPI_RESTORE_SWSMI
28 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
29 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
30#endif
31
32#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
33
34/*
35/// Extended PCI Address
36typedef struct _EXT_PCI_ADDR {
37 UINT32 Reg :16; ///< / PCI Register
38 UINT32 Func:3; ///< / PCI Function
39 UINT32 Dev :5; ///< / PCI Device
40 UINT32 Bus :8; ///< / PCI Address
41} EXT_PCI_ADDR;
42
43/// PCI Address
44typedef union _PCI_ADDR {
45 UINT32 ADDR; ///< / 32 bit Address
46 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
47} PCI_ADDR;
48*/
49#endif
50#define FIXUP_PTR(ptr) ptr
51
Martin Roth083504b2017-06-24 21:30:14 -0600[diff] [blame]52#if IS_ENABLED(CONFIG_SB800_IMC_FWM)
Martin Rothe899e512012-12-05 16:07:11 -0700[diff] [blame]53 #define IMC_ENABLE_OVER_WRITE 0x01
54#endif
55
Kerry Shefeed3292011-08-18 18:03:44 +0800[diff] [blame]56#include <console/console.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]57#include "AmdSbLib.h"
58#include "Amd.h"
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +0200[diff] [blame^]59#include <SB800.h>
60#include <SBTYPE.h>
61#include <ACPILIB.h>
62#include <SBDEF.h>
63#include <AMDSBLIB.h>
64#include <SBSUBFUN.h>
Kerry Shefeed3292011-08-18 18:03:44 +0800[diff] [blame]65#include "platform_cfg.h" /* mainboard specific configuration */
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +0200[diff] [blame^]66#include <OEM.h> /* platform default configuration */
67#include <AMD.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]68
69
70//------------------------------------------------------------------------------------------------------------------------//
71/**
Martin Roth3c3a50c2014-12-16 20:50:26 -0700[diff] [blame]72 * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]73 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
74 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
75 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
76 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
77 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
78 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
79 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
80 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
81 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
82 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
83 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
84 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
85 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
86 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
87 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
88 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
89 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
Martin Roth3c3a50c2014-12-16 20:50:26 -0700[diff] [blame]90 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]91 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
92 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
93 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
94 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
95 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
96 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
97 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
98 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
99 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
100 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
101 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
102 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
103 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
104 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
105 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
106 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
107 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
108 */
109#define SB_CIMx_PARAMETER 0x02
110
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]111// Generic
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]112#define cimSpreadSpectrumDefault TRUE
113#define cimSpreadSpectrumTypeDefault 0x00 // Normal
114#define cimHpetTimerDefault TRUE
115#define cimHpetMsiDisDefault FALSE // Enable
116#define cimIrConfigDefault 0x00 // Disable
Scott Duplichane78ae242011-05-15 21:18:59 +0000[diff] [blame]117#define cimSpiFastReadEnableDefault 0x01 // Enable
118#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
Kerry She6209c822011-08-18 18:44:00 +0800[diff] [blame]119#define cimSioHwmPortEnableDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]120// GPP/AB Controller
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]121#define cimNbSbGen2Default TRUE
122#define cimAlinkPhyPllPowerDownDefault TRUE
123#define cimResetCpuOnSyncFloodDefault TRUE
124#define cimGppGen2Default FALSE
125#define cimGppMemWrImproveDefault TRUE
126#define cimGppPortAspmDefault FALSE
127#define cimGppLaneReversalDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]128#define cimGppPhyPllPowerDownDefault TRUE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]129// USB Controller
130#define cimUsbPhyPowerDownDefault FALSE
131// GEC Controller
132#define cimSBGecDebugBusDefault FALSE
133#define cimSBGecPwrDefault 0x03
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]134// Sata Controller
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]135#define cimSataSetMaxGen2Default 0x00
136#define cimSATARefClkSelDefault 0x10
137#define cimSATARefDivSelDefault 0x80
138#define cimSataAggrLinkPmCapDefault TRUE
139#define cimSataPortMultCapDefault TRUE
140#define cimSataPscCapDefault 0x00 // Enable
141#define cimSataSscCapDefault 0x00 // Enable
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]142#define cimSataFisBasedSwitchingDefault FALSE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]143#define cimSataCccSupportDefault FALSE
144#define cimSataClkAutoOffDefault FALSE
145#define cimNativepciesupportDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]146// Fusion Related
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]147#define cimAcDcMsgDefault FALSE
148#define cimTimerTickTrackDefault FALSE
149#define cimClockInterruptTagDefault FALSE
150#define cimOhciTrafficHandingDefault FALSE
151#define cimEhciTrafficHandingDefault FALSE
152#define cimFusionMsgCMultiCoreDefault FALSE
153#define cimFusionMsgCStageDefault FALSE
Stefan Reinauer971ebd82011-10-13 17:26:43 -0700[diff] [blame]154
155#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
Zheng Bao600784e2013-02-07 17:30:23 +0800[diff] [blame]156#include <spi-generic.h>
zbao01bd79f2012-03-23 11:36:08 +0800[diff] [blame]157
Elyes HAOUAS65fa5982014-07-22 23:12:38 +0200[diff] [blame]158#define BIOSRAM_INDEX 0xcd4
159#define BIOSRAM_DATA 0xcd5
zbao9bcdbf82012-04-05 13:18:49 +0800[diff] [blame]160
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]161#endif // _AMD_SBPLATFORM_H_