commit e78ae24eb1003f5fa22bd54365025dda78f37dda
author Scott Duplichan <scott@notabs.org> Sun May 15 21:18:59 2011 +0000
committer Marc Jones <marc.jones@amd.com> Sun May 15 21:18:59 2011 +0000
tree 513d2b271dd3b7cd8f5e46aa464c91f20183153a
parent 444c49c68c224ac5b88a6efd96d4d3b911347356

Configure CIMx to use 33 MHz fast mode for SPD read.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h

diff --git a/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
index 7efa5ec..93e1c31 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
@@ -116,8 +116,8 @@
 #define cimHpetTimerDefault             TRUE
 #define cimHpetMsiDisDefault            FALSE     // Enable
 #define cimIrConfigDefault              0x00      // Disable
-#define cimSpiFastReadEnableDefault     0x00      // Disable
-#define cimSpiFastReadSpeedDefault      0x00      // NULL
+#define cimSpiFastReadEnableDefault     0x01      // Enable
+#define cimSpiFastReadSpeedDefault      0x01      // 33 MHz
 // GPP/AB Controller 
 #define cimNbSbGen2Default              TRUE
 #define cimAlinkPhyPllPowerDownDefault  TRUE