Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 63e62b03a8385663bebff3bdee88327bb57b27fd / . / src / southbridge / amd / cimx_wrapper / sb800 / SBPLATFORM.h
blob: 7efa5ecfe262190aaff0189fde53df38e0f07f6f [file] [log] [blame]
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame^]1/*
2 *****************************************************************************
3 *
4 * This file is part of the coreboot project.
5 *
6 * Copyright (C) 2011 Advanced Micro Devices, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * ***************************************************************************
21 *
22 */
23
24#ifndef _AMD_SBPLATFORM_H_
25#define _AMD_SBPLATFORM_H_
26
27//#include "cbtypes.h"
28#ifdef NULL
29 #undef NULL
30#endif
31#define NULL 0
32
33typedef unsigned long long PLACEHOLDER;
34
35#ifndef SBOEM_ACPI_RESTORE_SWSMI
36 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
37 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
38#endif
39
40#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
41
42/*
43/// Extended PCI Address
44typedef struct _EXT_PCI_ADDR {
45 UINT32 Reg :16; ///< / PCI Register
46 UINT32 Func:3; ///< / PCI Function
47 UINT32 Dev :5; ///< / PCI Device
48 UINT32 Bus :8; ///< / PCI Address
49} EXT_PCI_ADDR;
50
51/// PCI Address
52typedef union _PCI_ADDR {
53 UINT32 ADDR; ///< / 32 bit Address
54 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
55} PCI_ADDR;
56*/
57#endif
58#define FIXUP_PTR(ptr) ptr
59
60#include "AmdSbLib.h"
61#include "Amd.h"
62#include "SB800.h"
63#include "SBTYPE.h"
64#include "ACPILIB.h"
65#include "SBDEF.h"
66#include "AMDSBLIB.h"
67#include "SBSUBFUN.h"
68#include "OEM.h"
69#include "AMD.h"
70
71
72//------------------------------------------------------------------------------------------------------------------------//
73/**
74 * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
75 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
76 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
77 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
78 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
79 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
80 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
81 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
82 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
83 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
84 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
85 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
86 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
87 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
88 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
89 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
90 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
91 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
92 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
93 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
94 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
95 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
96 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
97 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
98 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
99 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
100 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
101 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
102 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
103 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
104 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
105 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
106 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
107 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
108 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
109 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
110 */
111#define SB_CIMx_PARAMETER 0x02
112
113// Generic
114#define cimSpreadSpectrumDefault TRUE
115#define cimSpreadSpectrumTypeDefault 0x00 // Normal
116#define cimHpetTimerDefault TRUE
117#define cimHpetMsiDisDefault FALSE // Enable
118#define cimIrConfigDefault 0x00 // Disable
119#define cimSpiFastReadEnableDefault 0x00 // Disable
120#define cimSpiFastReadSpeedDefault 0x00 // NULL
121// GPP/AB Controller
122#define cimNbSbGen2Default TRUE
123#define cimAlinkPhyPllPowerDownDefault TRUE
124#define cimResetCpuOnSyncFloodDefault TRUE
125#define cimGppGen2Default FALSE
126#define cimGppMemWrImproveDefault TRUE
127#define cimGppPortAspmDefault FALSE
128#define cimGppLaneReversalDefault FALSE
129#define cimGppPhyPllPowerDownDefault TRUE
130// USB Controller
131#define cimUsbPhyPowerDownDefault FALSE
132// GEC Controller
133#define cimSBGecDebugBusDefault FALSE
134#define cimSBGecPwrDefault 0x03
135// Sata Controller
136#define cimSataSetMaxGen2Default 0x00
137#define cimSATARefClkSelDefault 0x10
138#define cimSATARefDivSelDefault 0x80
139#define cimSataAggrLinkPmCapDefault TRUE
140#define cimSataPortMultCapDefault TRUE
141#define cimSataPscCapDefault 0x00 // Enable
142#define cimSataSscCapDefault 0x00 // Enable
143#define cimSataFisBasedSwitchingDefault FALSE
144#define cimSataCccSupportDefault FALSE
145#define cimSataClkAutoOffDefault FALSE
146#define cimNativepciesupportDefault FALSE
147// Fusion Related
148#define cimAcDcMsgDefault FALSE
149#define cimTimerTickTrackDefault FALSE
150#define cimClockInterruptTagDefault FALSE
151#define cimOhciTrafficHandingDefault FALSE
152#define cimEhciTrafficHandingDefault FALSE
153#define cimFusionMsgCMultiCoreDefault FALSE
154#define cimFusionMsgCStageDefault FALSE
155#endif // _AMD_SBPLATFORM_H_