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review.coreboot.org / coreboot / 182dbdeac4b2489f8d03a47a79ab28ad556d9d21 / . / src / southbridge / amd / cimx / sb800 / SBPLATFORM.h
blob: 1addeea00c83f6f9cba907a52cdeb14ebcddceeb [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]3
Elyes HAOUAS65fa5982014-07-22 23:12:38 +0200[diff] [blame]4#ifndef _AMD_SBPLATFORM_H_
5#define _AMD_SBPLATFORM_H_
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]6
Aaron Durbind907a342014-01-30 22:20:01 -0600[diff] [blame]7#include <stddef.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]8
9typedef unsigned long long PLACEHOLDER;
10
11#ifndef SBOEM_ACPI_RESTORE_SWSMI
12 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
13 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
14#endif
15
16#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
17
18/*
19/// Extended PCI Address
20typedef struct _EXT_PCI_ADDR {
21 UINT32 Reg :16; ///< / PCI Register
22 UINT32 Func:3; ///< / PCI Function
23 UINT32 Dev :5; ///< / PCI Device
24 UINT32 Bus :8; ///< / PCI Address
25} EXT_PCI_ADDR;
26
27/// PCI Address
28typedef union _PCI_ADDR {
29 UINT32 ADDR; ///< / 32 bit Address
30 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
31} PCI_ADDR;
32*/
33#endif
34#define FIXUP_PTR(ptr) ptr
35
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]36#if CONFIG(SB800_IMC_FWM)
Martin Rothe899e512012-12-05 16:07:11 -0700[diff] [blame]37 #define IMC_ENABLE_OVER_WRITE 0x01
38#endif
39
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]40#include "AmdSbLib.h"
41#include "Amd.h"
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +0200[diff] [blame]42#include <SB800.h>
43#include <SBTYPE.h>
44#include <ACPILIB.h>
45#include <SBDEF.h>
46#include <AMDSBLIB.h>
47#include <SBSUBFUN.h>
Kerry Shefeed3292011-08-18 18:03:44 +0800[diff] [blame]48#include "platform_cfg.h" /* mainboard specific configuration */
Elyes HAOUAS19f5ba82018-10-14 14:52:06 +0200[diff] [blame]49#include <OEM.h> /* platform default configuration */
50#include <AMD.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]51
52
53//------------------------------------------------------------------------------------------------------------------------//
54/**
Martin Roth3c3a50c2014-12-16 20:50:26 -0700[diff] [blame]55 * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]56 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
57 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
58 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
59 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
60 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
61 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
62 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
63 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
64 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
65 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
66 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
67 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
68 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
69 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
70 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
71 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
72 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
Martin Roth3c3a50c2014-12-16 20:50:26 -0700[diff] [blame]73 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11)
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]74 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
75 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
76 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
77 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
78 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
79 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
80 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
81 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
82 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
83 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
84 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
85 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
86 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
87 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
88 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
89 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
90 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
91 */
92#define SB_CIMx_PARAMETER 0x02
93
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]94// Generic
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]95#define cimSpreadSpectrumDefault TRUE
96#define cimSpreadSpectrumTypeDefault 0x00 // Normal
97#define cimHpetTimerDefault TRUE
98#define cimHpetMsiDisDefault FALSE // Enable
99#define cimIrConfigDefault 0x00 // Disable
Scott Duplichane78ae242011-05-15 21:18:59 +0000[diff] [blame]100#define cimSpiFastReadEnableDefault 0x01 // Enable
101#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
Kerry She6209c822011-08-18 18:44:00 +0800[diff] [blame]102#define cimSioHwmPortEnableDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]103// GPP/AB Controller
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]104#define cimNbSbGen2Default TRUE
105#define cimAlinkPhyPllPowerDownDefault TRUE
106#define cimResetCpuOnSyncFloodDefault TRUE
107#define cimGppGen2Default FALSE
108#define cimGppMemWrImproveDefault TRUE
109#define cimGppPortAspmDefault FALSE
110#define cimGppLaneReversalDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]111#define cimGppPhyPllPowerDownDefault TRUE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]112// USB Controller
113#define cimUsbPhyPowerDownDefault FALSE
114// GEC Controller
115#define cimSBGecDebugBusDefault FALSE
116#define cimSBGecPwrDefault 0x03
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]117// Sata Controller
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]118#define cimSataSetMaxGen2Default 0x00
119#define cimSATARefClkSelDefault 0x10
120#define cimSATARefDivSelDefault 0x80
121#define cimSataAggrLinkPmCapDefault TRUE
122#define cimSataPortMultCapDefault TRUE
123#define cimSataPscCapDefault 0x00 // Enable
124#define cimSataSscCapDefault 0x00 // Enable
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]125#define cimSataFisBasedSwitchingDefault FALSE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]126#define cimSataCccSupportDefault FALSE
127#define cimSataClkAutoOffDefault FALSE
128#define cimNativepciesupportDefault FALSE
Stefan Reinauer5ff7c132011-10-31 12:56:45 -0700[diff] [blame]129// Fusion Related
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]130#define cimAcDcMsgDefault FALSE
131#define cimTimerTickTrackDefault FALSE
132#define cimClockInterruptTagDefault FALSE
133#define cimOhciTrafficHandingDefault FALSE
134#define cimEhciTrafficHandingDefault FALSE
135#define cimFusionMsgCMultiCoreDefault FALSE
136#define cimFusionMsgCStageDefault FALSE
Stefan Reinauer971ebd82011-10-13 17:26:43 -0700[diff] [blame]137
138#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
Zheng Bao600784e2013-02-07 17:30:23 +0800[diff] [blame]139#include <spi-generic.h>
zbao01bd79f2012-03-23 11:36:08 +0800[diff] [blame]140
Elyes HAOUAS65fa5982014-07-22 23:12:38 +0200[diff] [blame]141#define BIOSRAM_INDEX 0xcd4
142#define BIOSRAM_DATA 0xcd5
zbao9bcdbf82012-04-05 13:18:49 +0800[diff] [blame]143
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]144#endif // _AMD_SBPLATFORM_H_