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review.coreboot.org / coreboot / 971ebd8ee6de9ac30b208da53862918e506ac5e7 / . / src / southbridge / amd / cimx / sb800 / SBPLATFORM.h
blob: d7317a23a20747db39d6b2175989fe1f38383a19 [file] [log] [blame]
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]1/*
2 *****************************************************************************
3 *
4 * This file is part of the coreboot project.
5 *
6 * Copyright (C) 2011 Advanced Micro Devices, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * ***************************************************************************
21 *
22 */
23
24#ifndef _AMD_SBPLATFORM_H_
25#define _AMD_SBPLATFORM_H_
26
27//#include "cbtypes.h"
28#ifdef NULL
29 #undef NULL
30#endif
31#define NULL 0
32
33typedef unsigned long long PLACEHOLDER;
34
35#ifndef SBOEM_ACPI_RESTORE_SWSMI
36 #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
37 #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
38#endif
39
40#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
41
42/*
43/// Extended PCI Address
44typedef struct _EXT_PCI_ADDR {
45 UINT32 Reg :16; ///< / PCI Register
46 UINT32 Func:3; ///< / PCI Function
47 UINT32 Dev :5; ///< / PCI Device
48 UINT32 Bus :8; ///< / PCI Address
49} EXT_PCI_ADDR;
50
51/// PCI Address
52typedef union _PCI_ADDR {
53 UINT32 ADDR; ///< / 32 bit Address
54 EXT_PCI_ADDR Addr; ///< / Extended PCI Address
55} PCI_ADDR;
56*/
57#endif
58#define FIXUP_PTR(ptr) ptr
59
Kerry Shefeed3292011-08-18 18:03:44 +0800[diff] [blame]60#include <console/console.h>
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]61#include "AmdSbLib.h"
62#include "Amd.h"
63#include "SB800.h"
64#include "SBTYPE.h"
65#include "ACPILIB.h"
66#include "SBDEF.h"
67#include "AMDSBLIB.h"
68#include "SBSUBFUN.h"
Kerry Shefeed3292011-08-18 18:03:44 +0800[diff] [blame]69#include "platform_cfg.h" /* mainboard specific configuration */
70#include "OEM.h" /* platform default configuration */
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]71#include "AMD.h"
72
73
74//------------------------------------------------------------------------------------------------------------------------//
75/**
76 * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over
77 * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable
78 * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal
79 * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable
80 * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
81 * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)
82 * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable
83 * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)
84 * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable
85 * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
86 * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable
87 * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable
88 * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable
89 * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable
90 * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable
91 * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable
92 * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable
93 * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable
94 * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)
95 * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)
96 * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz
97 * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable
98 * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable
99 * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
100 * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)
101 * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable
102 * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable
103 * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable
104 * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable
105 * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable
106 * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable
107 * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable
108 * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
109 * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable
110 * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable
111 * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable
112 */
113#define SB_CIMx_PARAMETER 0x02
114
115// Generic
116#define cimSpreadSpectrumDefault TRUE
117#define cimSpreadSpectrumTypeDefault 0x00 // Normal
118#define cimHpetTimerDefault TRUE
119#define cimHpetMsiDisDefault FALSE // Enable
120#define cimIrConfigDefault 0x00 // Disable
Scott Duplichane78ae242011-05-15 21:18:59 +0000[diff] [blame]121#define cimSpiFastReadEnableDefault 0x01 // Enable
122#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
Kerry She6209c822011-08-18 18:44:00 +0800[diff] [blame]123#define cimSioHwmPortEnableDefault FALSE
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]124// GPP/AB Controller
125#define cimNbSbGen2Default TRUE
126#define cimAlinkPhyPllPowerDownDefault TRUE
127#define cimResetCpuOnSyncFloodDefault TRUE
128#define cimGppGen2Default FALSE
129#define cimGppMemWrImproveDefault TRUE
130#define cimGppPortAspmDefault FALSE
131#define cimGppLaneReversalDefault FALSE
132#define cimGppPhyPllPowerDownDefault TRUE
133// USB Controller
134#define cimUsbPhyPowerDownDefault FALSE
135// GEC Controller
136#define cimSBGecDebugBusDefault FALSE
137#define cimSBGecPwrDefault 0x03
138// Sata Controller
139#define cimSataSetMaxGen2Default 0x00
140#define cimSATARefClkSelDefault 0x10
141#define cimSATARefDivSelDefault 0x80
142#define cimSataAggrLinkPmCapDefault TRUE
143#define cimSataPortMultCapDefault TRUE
144#define cimSataPscCapDefault 0x00 // Enable
145#define cimSataSscCapDefault 0x00 // Enable
146#define cimSataFisBasedSwitchingDefault FALSE
147#define cimSataCccSupportDefault FALSE
148#define cimSataClkAutoOffDefault FALSE
149#define cimNativepciesupportDefault FALSE
150// Fusion Related
151#define cimAcDcMsgDefault FALSE
152#define cimTimerTickTrackDefault FALSE
153#define cimClockInterruptTagDefault FALSE
154#define cimOhciTrafficHandingDefault FALSE
155#define cimEhciTrafficHandingDefault FALSE
156#define cimFusionMsgCMultiCoreDefault FALSE
157#define cimFusionMsgCStageDefault FALSE
Stefan Reinauer971ebd82011-10-13 17:26:43 -0700[diff] [blame^]158
159#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
160
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame]161#endif // _AMD_SBPLATFORM_H_