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Angel Pons6e5aabd2020-03-23 23:44:42 +01001## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauer00636b02012-04-04 00:08:51 +02002
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -07003config NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02004 bool
Arthur Heymans7539b8c2017-12-24 10:42:57 +01005 select CACHE_MRC_SETTINGS
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02006 select CPU_INTEL_MODEL_206AX
7 select HAVE_DEBUG_RAM_SETUP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01008 select INTEL_GMA_ACPI
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02009
Nico Huber772a1542019-05-10 16:48:14 +020010if NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010011
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010012config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
13 bool
14 default n
15 help
16 Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
17
18config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
19 depends on VBOOT
20 depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE
21 bool "Start verstage in bootblock"
22 default y
23 select VBOOT_STARTS_IN_BOOTBLOCK
24 select VBOOT_SEPARATE_VERSTAGE
25 help
26 Sandy Bridge can either start verstage in a separate stage
27 right after the bootblock has run or it can start it
28 after romstage for compatibility reasons.
29 Sandy Bridge however uses a mrc.bin to initialize memory which
30 needs to be located at a fixed offset. Therefore even with
31 a separate verstage starting after the bootblock that same
32 binary is used meaning a jump is made from RW to the RO region
33 and back to the RW region after the binary is done.
34
Kyösti Mälkki11c6b8b2021-02-10 19:22:31 +020035config CHROMEOS
36 select CHROMEOS_RAMOOPS_DYNAMIC
37
Julius Werner1210b412017-03-27 19:26:32 -070038config VBOOT
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010039 select VBOOT_MUST_REQUEST_DISPLAY
40 select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070041
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010042config USE_NATIVE_RAMINIT
43 bool "Use native raminit"
44 default y
45 help
46 Select if you want to use coreboot implementation of raminit rather than
47 System Agent/MRC.bin. You should answer Y.
Stefan Reinauer00636b02012-04-04 00:08:51 +020048
Patrick Rudolphb794a692017-08-08 13:13:51 +020049config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
50 bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
51 default n
52 depends on USE_NATIVE_RAMINIT
53 help
54 Ignore the mainboard's vendor programmed fuses that might limit the
55 maximum DRAM frequency. By selecting this option the fuses will be
56 ignored and the only limits on DRAM frequency are set by RAM's SPD and
57 hard fuses in southbridge's clockgen.
58 Disabled by default as it might causes system instability.
59 Handle with care!
60
Vagiz Trakhanov771be482017-10-02 10:02:35 +000061config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
62 bool "Ignore XMP profile max DIMMs per channel"
63 default n
64 depends on USE_NATIVE_RAMINIT
65 help
66 Ignore the max DIMMs per channel restriciton defined in XMP profiles.
67 Disabled by default as it might cause system instability.
68 Handle with care!
69
Angel Pons3170e9c2020-12-12 16:22:18 +010070config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
71 bool "Ignore XMP profile requested voltage"
72 default n
73 depends on USE_NATIVE_RAMINIT
74 help
75 Native raminit only supports 1.5V operation, but there are DIMMs
76 which request 1.65V operation in XMP profiles. This option allows
77 raminit to use these XMP profiles anyway, instead of falling back
78 to non-XMP settings.
79 Disabled by default because it allows forcing memory to run out of
80 specification. Consider this to be an overclocking option.
81 Handle with care!
82
Martin Roth59ff3402016-02-09 09:06:46 -070083config CBFS_SIZE
84 hex
85 default 0x100000
86
Stefan Reinauer00636b02012-04-04 00:08:51 +020087config VGA_BIOS_ID
88 string
89 default "8086,0106"
90
Nico Huber2b5c0212017-07-29 01:10:49 +020091config MMCONF_BASE_ADDRESS
Nico Huber2b5c0212017-07-29 01:10:49 +020092 default 0xf0000000
93 help
Arthur Heymans742a0e92018-01-29 16:34:46 +010094 The MRC blob requires it to be at 0xf0000000.
Nico Huber2b5c0212017-07-29 01:10:49 +020095
Angel Pons10f9b832021-01-20 14:58:32 +010096config MMCONF_BUS_NUMBER
97 int
98 default 64
99
Stefan Reinauer00636b02012-04-04 00:08:51 +0200100config DCACHE_RAM_BASE
101 hex
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300102 default 0xfefe0000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200103
Arthur Heymans67d59d12019-11-16 20:06:20 +0100104config DCACHE_BSP_STACK_SIZE
105 hex
Arthur Heymans8d821092019-11-25 06:56:04 +0100106 default 0x10000
107 help
108 The amount of BSP stack anticipated in bootblock and
109 other stages.
Arthur Heymans01c83a22019-06-05 13:36:55 +0200110
111if USE_NATIVE_RAMINIT
112
Stefan Reinauer00636b02012-04-04 00:08:51 +0200113config DCACHE_RAM_SIZE
114 hex
115 default 0x20000
116
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300117config DCACHE_RAM_MRC_VAR_SIZE
118 hex
119 default 0x0
120
Angel Pons09fc4b92020-11-19 12:02:07 +0100121config RAMINIT_ALWAYS_ALLOW_DLL_OFF
122 bool "Also enable memory DLL-off mode on desktops and servers"
123 default n
124 help
125 If enabled, allow enabling DLL-off mode for platforms other than
126 mobile. Saves power at the expense of higher exit latencies. Has
127 no effect on mobile platforms, where DLL-off is always allowed.
128 Power down is disabled for stability when running at high clocks.
129
Patrick Rudolphdd662872017-10-28 18:20:11 +0200130config RAMINIT_ENABLE_ECC
131 bool "Enable ECC if supported"
132 default y
133 help
134 Enable ECC if supported by both, host and RAM.
135
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300136endif # USE_NATIVE_RAMINIT
137
138if !USE_NATIVE_RAMINIT
139
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300140config DCACHE_RAM_SIZE
141 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200142 default 0x17000
Kyösti Mälkkifbdb0852013-07-01 11:21:53 +0300143
Stefan Reinauer00636b02012-04-04 00:08:51 +0200144config DCACHE_RAM_MRC_VAR_SIZE
145 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200146 default 0x9000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200147
Stefan Reinauer00636b02012-04-04 00:08:51 +0200148config MRC_FILE
149 string "Intel System Agent path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200150 default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
Stefan Reinauer00636b02012-04-04 00:08:51 +0200151 help
152 The path and filename of the file to use as System Agent
153 binary.
154
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300155endif # !USE_NATIVE_RAMINIT
Kyösti Mälkki0306e6a2016-06-23 12:41:40 +0300156
Nico Huber612a8672019-02-19 19:11:29 +0100157config INTEL_GMA_BCLV_OFFSET
158 default 0x48254
159
Angel Ponsd9e58dc2021-01-20 01:22:20 +0100160config FIXED_MCHBAR_MMIO_BASE
161 default 0xfed10000
162
163config FIXED_DMIBAR_MMIO_BASE
164 default 0xfed18000
165
166config FIXED_EPBAR_MMIO_BASE
167 default 0xfed19000
168
Stefan Reinauer00636b02012-04-04 00:08:51 +0200169endif