Blame - src/soc/intel/xeon_sp/cpx/Kconfig - coreboot

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Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	1	## SPDX-License-Identifier: GPL-2.0-only
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	2
				3	if SOC_INTEL_COOPERLAKE_SP
				4
Arthur Heymans	86d195b	2020-12-11 09:46:03 +0100	[diff] [blame]	5	config SOC_SPECIFIC_OPTIONS
				6	def_bool y
Arthur Heymans	ffa61b0	2021-09-07 14:16:50 +0200	[diff] [blame]	7	select HAVE_INTEL_FSP_REPO
Arthur Heymans	86d195b	2020-12-11 09:46:03 +0100	[diff] [blame]	8
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	9	config FSP_HEADER_PATH
Arthur Heymans	ffa61b0	2021-09-07 14:16:50 +0200	[diff] [blame]	10	default "3rdparty/fsp/CedarIslandFspBinPkg/Include"
				11
				12	config FSP_FD_PATH
				13	default "3rdparty/fsp/CedarIslandFspBinPkg/Fsp.fd"
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	14
				15	config MAX_SOCKET
				16	int
				17	default 2
				18
				19	config MAX_CPUS
				20	int
Andrey Petrov	e37d1f7	2020-04-20 21:11:51 -0700	[diff] [blame]	21	default 255
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	22
				23	config PCR_BASE_ADDRESS
				24	hex
				25	default 0xfd000000
				26	help
				27	This option allows you to select MMIO Base Address of sideband bus.
				28
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	29	config DCACHE_RAM_BASE
				30	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	31	default 0xfe800000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	32
				33	config DCACHE_RAM_SIZE
				34	hex
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	35	default 0x1fff00
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	36	help
				37	The size of the cache-as-ram region required during bootblock
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	38	and/or romstage. FSP-T reserves the upper 0x100 for
				39	FspReservedBuffer.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	40
				41	config DCACHE_BSP_STACK_SIZE
				42	hex
Arthur Heymans	7a5c369	2021-01-04 12:49:39 +0100	[diff] [blame]	43	default 0x40000
Jonathan Zhang	d4efb33	2020-07-22 12:39:40 -0700	[diff] [blame]	44	help
				45	The amount of anticipated stack usage in CAR by bootblock and
				46	other stages. It needs to include FSP-M stack requirement and
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	47	CB romstage stack requirement. The integration documentation
Arthur Heymans	7a5c369	2021-01-04 12:49:39 +0100	[diff] [blame]	48	says this needs to be 256KiB.
				49
				50	config FSP_M_RC_HEAP_SIZE
				51	hex
				52	default 0x130000
				53	help
				54	On xeon_sp/cpx FSP-M has two separate heap managers, one regular
				55	whose size and base are controllable via the StackBase and
				56	StackSize UPDs and a 'rc' heap manager that is statically
				57	allocated at 0xfe800000 (the CAR base) and consumes about 0x130000
				58	bytes of memory.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	59
				60	config CPU_MICROCODE_CBFS_LOC
				61	hex
				62	default 0xfff0fdc0
				63
				64	config CPU_MICROCODE_CBFS_LEN
				65	hex
				66	default 0x7C00
				67
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	68	config HEAP_SIZE
				69	hex
				70	default 0x80000
				71
Jonathan Zhang	4337a9a	2020-07-31 17:35:25 -0700	[diff] [blame]	72	config STACK_SIZE
				73	hex
				74	default 0x4000
				75
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	76	config FSP_TEMP_RAM_SIZE
				77	hex
				78	depends on FSP_USES_CB_STACK
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	79	default 0x40000
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	80	help
				81	The amount of anticipated heap usage in CAR by FSP.
				82	Refer to Platform FSP integration guide document to know
Arthur Heymans	b38d6bb	2020-10-28 18:24:56 +0100	[diff] [blame]	83	the exact FSP requirement for Heap setup. The FSP integration
				84	documentation says this needs to be at least 128KiB, but practice
				85	show this needs to be 256KiB or more.
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	86
Rocky Phagura	17a798b	2020-10-08 13:32:41 -0700	[diff] [blame]	87	config IED_REGION_SIZE
				88	hex
				89	default 0x400000
				90
Johnny Lin	c05aa26	2021-06-22 11:35:41 +0800	[diff] [blame]	91	config IFD_CHIPSET
				92	string
				93	default "lbg"
				94
Andrey Petrov	cf270f0	2020-04-30 13:36:38 -0700	[diff] [blame]	95	config SOC_INTEL_COMMON_BLOCK_P2SB
				96	def_bool y
				97
Jingle Hsu	a41b12c	2020-08-11 20:48:45 +0800	[diff] [blame]	98	config CPU_BCLK_MHZ
				99	int
				100	default 100
				101
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame]	102	# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
				103	# Default value is set to one socket, full config.
				104	config DIMM_MAX
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame]	105	default 12
				106
				107	# DDR4
				108	config DIMM_SPD_SIZE
Jonathan Zhang	decf7dc	2020-07-27 15:26:30 -0700	[diff] [blame]	109	default 512
				110
Arthur Heymans	9059a89	2020-10-23 11:08:41 +0200	[diff] [blame]	111	if INTEL_TXT
				112
				113	config INTEL_TXT_SINIT_SIZE
				114	hex
				115	default 0x50000
				116	help
				117	According to document number 572782 this needs to be 256KiB
				118	for the SINIT module and 64KiB for SINIT data.
				119
				120	config INTEL_TXT_HEAP_SIZE
				121	hex
				122	default 0xf0000
				123	help
				124	This must be 960KiB according to 572782.
				125
				126	endif # INTEL_TXT
				127
Andrey Petrov	2e41075	2020-03-20 12:08:32 -0700	[diff] [blame]	128	endif