Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <cpu/cpu.h> |
| 7 | #include <cpu/x86/mtrr.h> |
| 8 | #include <cpu/x86/msr.h> |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 9 | #include <cpu/x86/mp.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | #include <cpu/x86/lapic.h> |
| 11 | #include <cpu/intel/microcode.h> |
Kyösti Mälkki | faf20d3 | 2019-08-14 05:41:41 +0300 | [diff] [blame] | 12 | #include <cpu/intel/smm_reloc.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include <cpu/intel/speedstep.h> |
| 14 | #include <cpu/intel/turbo.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | #include <cpu/x86/name.h> |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 16 | #include <delay.h> |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 17 | #include <northbridge/intel/haswell/haswell.h> |
| 18 | #include <southbridge/intel/lynxpoint/pch.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 19 | #include <cpu/intel/common/common.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | #include "haswell.h" |
| 21 | #include "chip.h" |
| 22 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 23 | #define MWAIT_RES(state, sub_state) \ |
| 24 | { \ |
| 25 | .addrl = (((state) << 4) | (sub_state)), \ |
| 26 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 27 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 28 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 29 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 30 | } |
| 31 | |
| 32 | static acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 33 | [C_STATE_C0] = { }, |
| 34 | [C_STATE_C1] = { |
| 35 | .latency = 0, |
| 36 | .power = 1000, |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 37 | .resource = MWAIT_RES(0, 0), |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 38 | }, |
| 39 | [C_STATE_C1E] = { |
| 40 | .latency = 0, |
| 41 | .power = 1000, |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 42 | .resource = MWAIT_RES(0, 1), |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 43 | }, |
| 44 | [C_STATE_C3] = { |
| 45 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 46 | .power = 900, |
| 47 | .resource = MWAIT_RES(1, 0), |
| 48 | }, |
| 49 | [C_STATE_C6_SHORT_LAT] = { |
| 50 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 51 | .power = 800, |
| 52 | .resource = MWAIT_RES(2, 0), |
| 53 | }, |
| 54 | [C_STATE_C6_LONG_LAT] = { |
| 55 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 56 | .power = 800, |
| 57 | .resource = MWAIT_RES(2, 1), |
| 58 | }, |
| 59 | [C_STATE_C7_SHORT_LAT] = { |
| 60 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 61 | .power = 700, |
| 62 | .resource = MWAIT_RES(3, 0), |
| 63 | }, |
| 64 | [C_STATE_C7_LONG_LAT] = { |
| 65 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 66 | .power = 700, |
| 67 | .resource = MWAIT_RES(3, 1), |
| 68 | }, |
| 69 | [C_STATE_C7S_SHORT_LAT] = { |
| 70 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 71 | .power = 700, |
| 72 | .resource = MWAIT_RES(3, 2), |
| 73 | }, |
| 74 | [C_STATE_C7S_LONG_LAT] = { |
| 75 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 76 | .power = 700, |
| 77 | .resource = MWAIT_RES(3, 3), |
| 78 | }, |
| 79 | [C_STATE_C8] = { |
| 80 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
| 81 | .power = 600, |
| 82 | .resource = MWAIT_RES(4, 0), |
| 83 | }, |
| 84 | [C_STATE_C9] = { |
| 85 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
| 86 | .power = 500, |
| 87 | .resource = MWAIT_RES(5, 0), |
| 88 | }, |
| 89 | [C_STATE_C10] = { |
| 90 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
| 91 | .power = 400, |
| 92 | .resource = MWAIT_RES(6, 0), |
| 93 | }, |
| 94 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 95 | |
| 96 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 97 | static const u8 power_limit_time_sec_to_msr[] = { |
| 98 | [0] = 0x00, |
| 99 | [1] = 0x0a, |
| 100 | [2] = 0x0b, |
| 101 | [3] = 0x4b, |
| 102 | [4] = 0x0c, |
| 103 | [5] = 0x2c, |
| 104 | [6] = 0x4c, |
| 105 | [7] = 0x6c, |
| 106 | [8] = 0x0d, |
| 107 | [10] = 0x2d, |
| 108 | [12] = 0x4d, |
| 109 | [14] = 0x6d, |
| 110 | [16] = 0x0e, |
| 111 | [20] = 0x2e, |
| 112 | [24] = 0x4e, |
| 113 | [28] = 0x6e, |
| 114 | [32] = 0x0f, |
| 115 | [40] = 0x2f, |
| 116 | [48] = 0x4f, |
| 117 | [56] = 0x6f, |
| 118 | [64] = 0x10, |
| 119 | [80] = 0x30, |
| 120 | [96] = 0x50, |
| 121 | [112] = 0x70, |
| 122 | [128] = 0x11, |
| 123 | }; |
| 124 | |
| 125 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 126 | static const u8 power_limit_time_msr_to_sec[] = { |
| 127 | [0x00] = 0, |
| 128 | [0x0a] = 1, |
| 129 | [0x0b] = 2, |
| 130 | [0x4b] = 3, |
| 131 | [0x0c] = 4, |
| 132 | [0x2c] = 5, |
| 133 | [0x4c] = 6, |
| 134 | [0x6c] = 7, |
| 135 | [0x0d] = 8, |
| 136 | [0x2d] = 10, |
| 137 | [0x4d] = 12, |
| 138 | [0x6d] = 14, |
| 139 | [0x0e] = 16, |
| 140 | [0x2e] = 20, |
| 141 | [0x4e] = 24, |
| 142 | [0x6e] = 28, |
| 143 | [0x0f] = 32, |
| 144 | [0x2f] = 40, |
| 145 | [0x4f] = 48, |
| 146 | [0x6f] = 56, |
| 147 | [0x10] = 64, |
| 148 | [0x30] = 80, |
| 149 | [0x50] = 96, |
| 150 | [0x70] = 112, |
| 151 | [0x11] = 128, |
| 152 | }; |
| 153 | |
Angel Pons | 5d92aa5 | 2020-10-14 00:02:37 +0200 | [diff] [blame] | 154 | /* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate |
| 155 | * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 156 | * when a core is woken up. */ |
| 157 | static int pcode_ready(void) |
| 158 | { |
| 159 | int wait_count; |
| 160 | const int delay_step = 10; |
| 161 | |
| 162 | wait_count = 0; |
| 163 | do { |
| 164 | if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) |
| 165 | return 0; |
| 166 | wait_count += delay_step; |
| 167 | udelay(delay_step); |
| 168 | } while (wait_count < 1000); |
| 169 | |
| 170 | return -1; |
| 171 | } |
| 172 | |
| 173 | static void calibrate_24mhz_bclk(void) |
| 174 | { |
| 175 | int err_code; |
| 176 | |
| 177 | if (pcode_ready() < 0) { |
| 178 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 179 | return; |
| 180 | } |
| 181 | |
| 182 | /* A non-zero value initiates the PCODE calibration. */ |
| 183 | MCHBAR32(BIOS_MAILBOX_DATA) = ~0; |
| 184 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| 185 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; |
| 186 | |
| 187 | if (pcode_ready() < 0) { |
| 188 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 189 | return; |
| 190 | } |
| 191 | |
| 192 | err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; |
| 193 | |
Angel Pons | 5d92aa5 | 2020-10-14 00:02:37 +0200 | [diff] [blame] | 194 | printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 195 | err_code); |
| 196 | |
| 197 | /* Read the calibrated value. */ |
| 198 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| 199 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; |
| 200 | |
| 201 | if (pcode_ready() < 0) { |
| 202 | printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); |
| 203 | return; |
| 204 | } |
| 205 | |
Angel Pons | 5d92aa5 | 2020-10-14 00:02:37 +0200 | [diff] [blame] | 206 | printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 207 | MCHBAR32(BIOS_MAILBOX_DATA)); |
| 208 | } |
| 209 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 210 | static u32 pcode_mailbox_read(u32 command) |
| 211 | { |
| 212 | if (pcode_ready() < 0) { |
| 213 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | /* Send command and start transaction */ |
| 218 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; |
| 219 | |
| 220 | if (pcode_ready() < 0) { |
| 221 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 222 | return 0; |
| 223 | } |
| 224 | |
| 225 | /* Read mailbox */ |
| 226 | return MCHBAR32(BIOS_MAILBOX_DATA); |
| 227 | } |
| 228 | |
Angel Pons | 1c7ba62 | 2020-10-29 00:01:29 +0100 | [diff] [blame] | 229 | static int pcode_mailbox_write(u32 command, u32 data) |
| 230 | { |
| 231 | if (pcode_ready() < 0) { |
| 232 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 233 | return -1; |
| 234 | } |
| 235 | |
| 236 | MCHBAR32(BIOS_MAILBOX_DATA) = data; |
| 237 | |
| 238 | /* Send command and start transaction */ |
| 239 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; |
| 240 | |
| 241 | if (pcode_ready() < 0) { |
| 242 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 243 | return -1; |
| 244 | } |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 249 | static void initialize_vr_config(void) |
| 250 | { |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 251 | struct cpu_vr_config vr_config = { 0 }; |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 252 | msr_t msr; |
| 253 | |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 254 | const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 255 | |
| 256 | if (lapic && lapic->chip_info) { |
| 257 | const struct cpu_intel_haswell_config *conf = lapic->chip_info; |
| 258 | |
| 259 | vr_config = conf->vr_config; |
| 260 | } |
| 261 | |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 262 | printk(BIOS_DEBUG, "Initializing VR config.\n"); |
| 263 | |
| 264 | /* Configure VR_CURRENT_CONFIG. */ |
| 265 | msr = rdmsr(MSR_VR_CURRENT_CONFIG); |
| 266 | /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid |
| 267 | * on ULT systems. */ |
| 268 | msr.hi &= 0xc0000000; |
| 269 | msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ |
| 270 | msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ |
Angel Pons | 9dcd1c1 | 2020-10-28 22:41:26 +0100 | [diff] [blame] | 271 | msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 272 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 273 | if (haswell_is_ult()) |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 274 | msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ |
| 275 | /* Leave the max instantaneous current limit (12:0) to default. */ |
| 276 | wrmsr(MSR_VR_CURRENT_CONFIG, msr); |
| 277 | |
| 278 | /* Configure VR_MISC_CONFIG MSR. */ |
| 279 | msr = rdmsr(MSR_VR_MISC_CONFIG); |
| 280 | /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ |
| 281 | msr.hi &= ~(0x3ff << (40 - 32)); |
| 282 | msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ |
| 283 | /* Set IOUT_OFFSET to 0. */ |
| 284 | msr.hi &= ~0xff; |
| 285 | /* Set exit ramp rate to fast. */ |
| 286 | msr.hi |= (1 << (50 - 32)); |
| 287 | /* Set entry ramp rate to slow. */ |
| 288 | msr.hi &= ~(1 << (51 - 32)); |
| 289 | /* Enable decay mode on C-state entry. */ |
| 290 | msr.hi |= (1 << (52 - 32)); |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 291 | /* Set the slow ramp rate */ |
Tristan Corrick | fdf907e | 2018-10-31 02:27:12 +1300 | [diff] [blame] | 292 | if (haswell_is_ult()) { |
Tristan Corrick | fdf907e | 2018-10-31 02:27:12 +1300 | [diff] [blame] | 293 | msr.hi &= ~(0x3 << (53 - 32)); |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 294 | /* Configure the C-state exit ramp rate. */ |
| 295 | if (vr_config.slow_ramp_rate_enable) { |
| 296 | /* Configured slow ramp rate. */ |
| 297 | msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32)); |
| 298 | /* Set exit ramp rate to slow. */ |
| 299 | msr.hi &= ~(1 << (50 - 32)); |
| 300 | } else { |
| 301 | /* Fast ramp rate / 4. */ |
| 302 | msr.hi |= (1 << (53 - 32)); |
| 303 | } |
Tristan Corrick | fdf907e | 2018-10-31 02:27:12 +1300 | [diff] [blame] | 304 | } |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 305 | /* Set MIN_VID (31:24) to allow CPU to have full control. */ |
| 306 | msr.lo &= ~0xff000000; |
Angel Pons | 242fd28 | 2020-10-28 23:48:56 +0100 | [diff] [blame] | 307 | msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24; |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 308 | wrmsr(MSR_VR_MISC_CONFIG, msr); |
| 309 | |
| 310 | /* Configure VR_MISC_CONFIG2 MSR. */ |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 311 | if (!haswell_is_ult()) |
| 312 | return; |
| 313 | |
| 314 | msr = rdmsr(MSR_VR_MISC_CONFIG2); |
| 315 | msr.lo &= ~0xffff; |
| 316 | /* Allow CPU to control minimum voltage completely (15:8) and |
Angel Pons | c86b119 | 2020-10-28 23:53:45 +0100 | [diff] [blame] | 317 | set the fast ramp voltage in 10mV steps. */ |
| 318 | if (cpu_family_model() == BROADWELL_FAMILY_ULT) |
| 319 | msr.lo |= 0x006a; /* 1.56V */ |
| 320 | else |
| 321 | msr.lo |= 0x006f; /* 1.60V */ |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 322 | wrmsr(MSR_VR_MISC_CONFIG2, msr); |
Angel Pons | 1c7ba62 | 2020-10-29 00:01:29 +0100 | [diff] [blame] | 323 | |
| 324 | /* Set C9/C10 VCC Min */ |
| 325 | pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f); |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 326 | } |
| 327 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 328 | static void configure_pch_power_sharing(void) |
| 329 | { |
| 330 | u32 pch_power, pch_power_ext, pmsync, pmsync2; |
| 331 | int i; |
| 332 | |
| 333 | /* Read PCH Power levels from PCODE */ |
| 334 | pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); |
| 335 | pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); |
| 336 | |
| 337 | printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 338 | pch_power, pch_power_ext); |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 339 | |
| 340 | pmsync = RCBA32(PMSYNC_CONFIG); |
| 341 | pmsync2 = RCBA32(PMSYNC_CONFIG2); |
| 342 | |
| 343 | /* Program PMSYNC_TPR_CONFIG PCH power limit values |
| 344 | * pmsync[0:4] = mailbox[0:5] |
| 345 | * pmsync[8:12] = mailbox[6:11] |
| 346 | * pmsync[16:20] = mailbox[12:17] |
| 347 | */ |
| 348 | for (i = 0; i < 3; i++) { |
| 349 | u32 level = pch_power & 0x3f; |
| 350 | pch_power >>= 6; |
| 351 | pmsync &= ~(0x1f << (i * 8)); |
| 352 | pmsync |= (level & 0x1f) << (i * 8); |
| 353 | } |
| 354 | RCBA32(PMSYNC_CONFIG) = pmsync; |
| 355 | |
| 356 | /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values |
| 357 | * pmsync2[0:4] = mailbox[23:18] |
| 358 | * pmsync2[8:12] = mailbox_ext[6:11] |
| 359 | * pmsync2[16:20] = mailbox_ext[12:17] |
| 360 | * pmsync2[24:28] = mailbox_ext[18:22] |
| 361 | */ |
| 362 | pmsync2 &= ~0x1f; |
| 363 | pmsync2 |= pch_power & 0x1f; |
| 364 | |
| 365 | for (i = 1; i < 4; i++) { |
| 366 | u32 level = pch_power_ext & 0x3f; |
| 367 | pch_power_ext >>= 6; |
| 368 | pmsync2 &= ~(0x1f << (i * 8)); |
| 369 | pmsync2 |= (level & 0x1f) << (i * 8); |
| 370 | } |
| 371 | RCBA32(PMSYNC_CONFIG2) = pmsync2; |
| 372 | } |
| 373 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 374 | int cpu_config_tdp_levels(void) |
| 375 | { |
| 376 | msr_t platform_info; |
| 377 | |
| 378 | /* Bits 34:33 indicate how many levels supported */ |
| 379 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 380 | return (platform_info.hi >> 1) & 3; |
| 381 | } |
| 382 | |
| 383 | /* |
| 384 | * Configure processor power limits if possible |
| 385 | * This must be done AFTER set of BIOS_RESET_CPL |
| 386 | */ |
| 387 | void set_power_limits(u8 power_limit_1_time) |
| 388 | { |
| 389 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 390 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame] | 391 | unsigned int power_unit; |
| 392 | unsigned int tdp, min_power, max_power, max_time; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 393 | u8 power_limit_1_val; |
| 394 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 395 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 396 | power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 397 | |
| 398 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 399 | return; |
| 400 | |
| 401 | /* Get units */ |
| 402 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 403 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 404 | |
| 405 | /* Get power defaults for this SKU */ |
| 406 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 407 | tdp = msr.lo & 0x7fff; |
| 408 | min_power = (msr.lo >> 16) & 0x7fff; |
| 409 | max_power = msr.hi & 0x7fff; |
| 410 | max_time = (msr.hi >> 16) & 0x7f; |
| 411 | |
| 412 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 413 | |
| 414 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 415 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 416 | |
| 417 | if (min_power > 0 && tdp < min_power) |
| 418 | tdp = min_power; |
| 419 | |
| 420 | if (max_power > 0 && tdp > max_power) |
| 421 | tdp = max_power; |
| 422 | |
| 423 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 424 | |
| 425 | /* Set long term power limit to TDP */ |
| 426 | limit.lo = 0; |
| 427 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 428 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 429 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 430 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 431 | |
| 432 | /* Set short term power limit to 1.25 * TDP */ |
| 433 | limit.hi = 0; |
| 434 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 435 | limit.hi |= PKG_POWER_LIMIT_EN; |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 436 | /* Power limit 2 time is only programmable on server SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 437 | |
| 438 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 439 | |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 440 | /* Set power limit values in MCHBAR as well */ |
| 441 | MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; |
| 442 | MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; |
| 443 | |
| 444 | /* Set DDR RAPL power limit by copying from MMIO to MSR */ |
| 445 | msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); |
| 446 | msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); |
| 447 | wrmsr(MSR_DDR_RAPL_LIMIT, msr); |
| 448 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 449 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 450 | if (cpu_config_tdp_levels()) { |
| 451 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 452 | limit.hi = 0; |
| 453 | limit.lo = msr.lo & 0xff; |
| 454 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 455 | } |
| 456 | } |
| 457 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 458 | static void configure_c_states(void) |
| 459 | { |
Angel Pons | c89d2a28 | 2020-10-28 22:23:02 +0100 | [diff] [blame] | 460 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 461 | |
| 462 | const bool timed_mwait_capable = !!(msr.hi & TIMED_MWAIT_SUPPORTED); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 463 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 464 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 465 | msr.lo |= (1 << 30); // Package c-state Undemotion Enable |
| 466 | msr.lo |= (1 << 29); // Package c-state Demotion Enable |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 467 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 468 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 469 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 470 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 471 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
Angel Pons | c89d2a28 | 2020-10-28 22:23:02 +0100 | [diff] [blame] | 472 | |
| 473 | if (timed_mwait_capable) |
| 474 | msr.lo |= (1 << 31); // Timed MWAIT Enable |
| 475 | |
Duncan Laurie | 1c09710 | 2013-05-07 13:19:56 -0700 | [diff] [blame] | 476 | /* The deepest package c-state defaults to factory-configured value. */ |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 477 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 478 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 479 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 480 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 481 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 482 | |
| 483 | msr = rdmsr(MSR_POWER_CTL); |
| 484 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 485 | msr.lo |= (1 << 1); // C1E Enable |
| 486 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 487 | wrmsr(MSR_POWER_CTL, msr); |
| 488 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 489 | /* C-state Interrupt Response Latency Control 0 - package C3 latency */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 490 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 491 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; |
| 492 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 493 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 494 | /* C-state Interrupt Response Latency Control 1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 495 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 496 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
| 497 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 498 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 499 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 500 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 501 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
| 502 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 503 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 504 | /* Only Haswell ULT supports the 3-5 latency response registers */ |
| 505 | if (!haswell_is_ult()) |
| 506 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 507 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 508 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 509 | msr.hi = 0; |
| 510 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; |
| 511 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 512 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 513 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 514 | msr.hi = 0; |
| 515 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; |
| 516 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 517 | |
| 518 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 519 | msr.hi = 0; |
| 520 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; |
| 521 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 522 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 523 | |
| 524 | static void configure_thermal_target(void) |
| 525 | { |
| 526 | struct cpu_intel_haswell_config *conf; |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 527 | struct device *lapic; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 528 | msr_t msr; |
| 529 | |
| 530 | /* Find pointer to CPU configuration */ |
| 531 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 532 | if (!lapic || !lapic->chip_info) |
| 533 | return; |
| 534 | conf = lapic->chip_info; |
| 535 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 536 | /* Set TCC activation offset if supported */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 537 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 538 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 539 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 540 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 541 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 542 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 543 | } |
| 544 | } |
| 545 | |
| 546 | static void configure_misc(void) |
| 547 | { |
| 548 | msr_t msr; |
| 549 | |
| 550 | msr = rdmsr(IA32_MISC_ENABLE); |
| 551 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 552 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 553 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 554 | wrmsr(IA32_MISC_ENABLE, msr); |
| 555 | |
| 556 | /* Disable Thermal interrupts */ |
| 557 | msr.lo = 0; |
| 558 | msr.hi = 0; |
| 559 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 560 | |
| 561 | /* Enable package critical interrupt only */ |
| 562 | msr.lo = 1 << 4; |
| 563 | msr.hi = 0; |
| 564 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 565 | } |
| 566 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 567 | static void set_max_ratio(void) |
| 568 | { |
| 569 | msr_t msr, perf_ctl; |
| 570 | |
| 571 | perf_ctl.hi = 0; |
| 572 | |
| 573 | /* Check for configurable TDP option */ |
Angel Pons | 053deb8 | 2020-10-28 22:40:02 +0100 | [diff] [blame] | 574 | if (get_turbo_state() == TURBO_ENABLED) { |
| 575 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 576 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 577 | } else if (cpu_config_tdp_levels()) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 578 | /* Set to nominal TDP ratio */ |
| 579 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 580 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 581 | } else { |
| 582 | /* Platform Info bits 15:8 give max ratio */ |
| 583 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 584 | perf_ctl.lo = msr.lo & 0xff00; |
| 585 | } |
| 586 | wrmsr(IA32_PERF_CTL, perf_ctl); |
| 587 | |
Angel Pons | f6cf4927 | 2020-09-25 01:14:24 +0200 | [diff] [blame] | 588 | printk(BIOS_DEBUG, "CPU: frequency set to %d\n", |
Angel Pons | ca96549 | 2020-10-28 19:15:36 +0100 | [diff] [blame] | 589 | ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 590 | } |
| 591 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 592 | static void configure_mca(void) |
| 593 | { |
| 594 | msr_t msr; |
| 595 | int i; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 596 | int num_banks; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 597 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 598 | msr = rdmsr(IA32_MCG_CAP); |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 599 | num_banks = msr.lo & 0xff; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 600 | msr.lo = msr.hi = 0; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 601 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 602 | * of these banks are core vs package scope. For now every CPU clears |
| 603 | * every bank. */ |
| 604 | for (i = 0; i < num_banks; i++) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 605 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| 606 | } |
| 607 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 608 | /* All CPUs including BSP will run the following function. */ |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 609 | static void cpu_core_init(struct device *cpu) |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 610 | { |
| 611 | /* Clear out pending MCEs */ |
| 612 | configure_mca(); |
| 613 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 614 | /* Enable the local CPU APICs */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 615 | enable_lapic_tpr(); |
| 616 | setup_lapic(); |
| 617 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 618 | /* Set virtualization based on Kconfig option */ |
Matt DeVillier | f9aed65 | 2018-12-15 15:57:33 -0600 | [diff] [blame] | 619 | set_vmx_and_lock(); |
Matt DeVillier | b2a14fb | 2014-07-07 18:48:16 -0500 | [diff] [blame] | 620 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 621 | /* Configure C States */ |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 622 | configure_c_states(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 623 | |
| 624 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 625 | configure_misc(); |
| 626 | |
| 627 | /* Thermal throttle activation offset */ |
| 628 | configure_thermal_target(); |
| 629 | |
| 630 | /* Enable Direct Cache Access */ |
| 631 | configure_dca_cap(); |
| 632 | |
| 633 | /* Set energy policy */ |
| 634 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 635 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 636 | /* Enable Turbo */ |
| 637 | enable_turbo(); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 638 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 639 | |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 640 | /* MP initialization support. */ |
| 641 | static const void *microcode_patch; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 642 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 643 | static void pre_mp_init(void) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 644 | { |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 645 | /* Setup MTRRs based on physical address size. */ |
| 646 | x86_setup_mtrrs_with_detect(); |
| 647 | x86_mtrr_check(); |
| 648 | |
| 649 | initialize_vr_config(); |
| 650 | |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 651 | if (!haswell_is_ult()) |
| 652 | return; |
| 653 | |
| 654 | calibrate_24mhz_bclk(); |
| 655 | configure_pch_power_sharing(); |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 656 | } |
| 657 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 658 | static int get_cpu_count(void) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 659 | { |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 660 | msr_t msr; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 661 | int num_threads; |
| 662 | int num_cores; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 663 | |
Elyes HAOUAS | a6a396d | 2019-05-26 13:25:30 +0200 | [diff] [blame] | 664 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 665 | num_threads = (msr.lo >> 0) & 0xffff; |
| 666 | num_cores = (msr.lo >> 16) & 0xffff; |
| 667 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 668 | num_cores, num_threads); |
| 669 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 670 | return num_threads; |
| 671 | } |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 672 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 673 | static void get_microcode_info(const void **microcode, int *parallel) |
| 674 | { |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 675 | microcode_patch = intel_microcode_find(); |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 676 | *microcode = microcode_patch; |
| 677 | *parallel = 1; |
| 678 | } |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 679 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 680 | static void per_cpu_smm_trigger(void) |
| 681 | { |
| 682 | /* Relocate the SMM handler. */ |
| 683 | smm_relocate(); |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 684 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 685 | /* After SMM relocation a 2nd microcode load is required. */ |
| 686 | intel_microcode_load_unlocked(microcode_patch); |
| 687 | } |
| 688 | |
| 689 | static void post_mp_init(void) |
| 690 | { |
Angel Pons | 053deb8 | 2020-10-28 22:40:02 +0100 | [diff] [blame] | 691 | /* Set Max Ratio */ |
| 692 | set_max_ratio(); |
| 693 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 694 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 695 | * start flowing. */ |
Kyösti Mälkki | 0778c86 | 2020-06-10 12:44:03 +0300 | [diff] [blame] | 696 | global_smi_enable(); |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 697 | |
| 698 | /* Lock down the SMRAM space. */ |
| 699 | smm_lock(); |
| 700 | } |
| 701 | |
| 702 | static const struct mp_ops mp_ops = { |
| 703 | .pre_mp_init = pre_mp_init, |
| 704 | .get_cpu_count = get_cpu_count, |
| 705 | .get_smm_info = smm_info, |
| 706 | .get_microcode_info = get_microcode_info, |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 707 | .pre_mp_smm_init = smm_initialize, |
| 708 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 709 | .relocation_handler = smm_relocation_handler, |
| 710 | .post_mp_init = post_mp_init, |
| 711 | }; |
| 712 | |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 713 | void mp_init_cpus(struct bus *cpu_bus) |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 714 | { |
Lee Leahy | 26eeb0f | 2017-03-15 18:08:50 -0700 | [diff] [blame] | 715 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 716 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 717 | } |
| 718 | |
| 719 | static struct device_operations cpu_dev_ops = { |
Angel Pons | 4c95f10 | 2020-10-28 19:38:12 +0100 | [diff] [blame] | 720 | .init = cpu_core_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 721 | }; |
| 722 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 723 | static const struct cpu_device_id cpu_table[] = { |
Angel Pons | 8b0636e | 2020-10-28 21:48:29 +0100 | [diff] [blame] | 724 | { X86_VENDOR_INTEL, CPUID_HASWELL_A0 }, |
| 725 | { X86_VENDOR_INTEL, CPUID_HASWELL_B0 }, |
| 726 | { X86_VENDOR_INTEL, CPUID_HASWELL_C0 }, |
| 727 | { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_B0 }, |
| 728 | { X86_VENDOR_INTEL, CPUID_HASWELL_ULT_C0 }, |
| 729 | { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_B0 }, |
| 730 | { X86_VENDOR_INTEL, CPUID_CRYSTALWELL_C0 }, |
Angel Pons | f542b7b | 2020-10-29 01:02:03 +0100 | [diff] [blame^] | 731 | { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, |
| 732 | { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_C0 }, |
| 733 | { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_D0 }, |
| 734 | { X86_VENDOR_INTEL, CPUID_BROADWELL_ULT_E0 }, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 735 | { 0, 0 }, |
| 736 | }; |
| 737 | |
| 738 | static const struct cpu_driver driver __cpu_driver = { |
| 739 | .ops = &cpu_dev_ops, |
| 740 | .id_table = cpu_table, |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 741 | .cstates = cstate_map, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 742 | }; |