Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <string.h> |
| 27 | #include <arch/acpi.h> |
| 28 | #include <cpu/cpu.h> |
| 29 | #include <cpu/x86/mtrr.h> |
| 30 | #include <cpu/x86/msr.h> |
| 31 | #include <cpu/x86/lapic.h> |
| 32 | #include <cpu/intel/microcode.h> |
| 33 | #include <cpu/intel/speedstep.h> |
| 34 | #include <cpu/intel/turbo.h> |
| 35 | #include <cpu/x86/cache.h> |
| 36 | #include <cpu/x86/name.h> |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 37 | #include <delay.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | #include <pc80/mc146818rtc.h> |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 39 | #include <northbridge/intel/haswell/haswell.h> |
| 40 | #include <southbridge/intel/lynxpoint/pch.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 41 | #include "haswell.h" |
| 42 | #include "chip.h" |
| 43 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 44 | /* Intel suggested latency times in units of 1024ns. */ |
| 45 | #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 |
| 46 | #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 |
| 47 | #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 |
| 48 | #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 |
| 49 | #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 |
| 50 | #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef |
| 51 | |
| 52 | #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ |
| 53 | (((1 << ((base)*5)) * (limit)) / 1000) |
| 54 | #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ |
| 55 | C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ |
| 56 | (IRTL_1024_NS >> 10)) |
| 57 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | /* |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 59 | * List of supported C-states in this processor. Only the ULT parts support C8, |
| 60 | * C9, and C10. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 61 | */ |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 62 | enum { |
| 63 | C_STATE_C0, /* 0 */ |
| 64 | C_STATE_C1, /* 1 */ |
| 65 | C_STATE_C1E, /* 2 */ |
| 66 | C_STATE_C3, /* 3 */ |
| 67 | C_STATE_C6_SHORT_LAT, /* 4 */ |
| 68 | C_STATE_C6_LONG_LAT, /* 5 */ |
| 69 | C_STATE_C7_SHORT_LAT, /* 6 */ |
| 70 | C_STATE_C7_LONG_LAT, /* 7 */ |
| 71 | C_STATE_C7S_SHORT_LAT, /* 8 */ |
| 72 | C_STATE_C7S_LONG_LAT, /* 9 */ |
| 73 | C_STATE_C8, /* 10 */ |
| 74 | C_STATE_C9, /* 11 */ |
| 75 | C_STATE_C10, /* 12 */ |
| 76 | NUM_C_STATES |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | }; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 78 | |
| 79 | #define MWAIT_RES(state, sub_state) \ |
| 80 | { \ |
| 81 | .addrl = (((state) << 4) | (sub_state)), \ |
| 82 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 83 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 84 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 85 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 86 | } |
| 87 | |
| 88 | static acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 89 | [C_STATE_C0] = { }, |
| 90 | [C_STATE_C1] = { |
| 91 | .latency = 0, |
| 92 | .power = 1000, |
| 93 | .resource = MWAIT_RES(0,0), |
| 94 | }, |
| 95 | [C_STATE_C1E] = { |
| 96 | .latency = 0, |
| 97 | .power = 1000, |
| 98 | .resource = MWAIT_RES(0,1), |
| 99 | }, |
| 100 | [C_STATE_C3] = { |
| 101 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 102 | .power = 900, |
| 103 | .resource = MWAIT_RES(1, 0), |
| 104 | }, |
| 105 | [C_STATE_C6_SHORT_LAT] = { |
| 106 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 107 | .power = 800, |
| 108 | .resource = MWAIT_RES(2, 0), |
| 109 | }, |
| 110 | [C_STATE_C6_LONG_LAT] = { |
| 111 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 112 | .power = 800, |
| 113 | .resource = MWAIT_RES(2, 1), |
| 114 | }, |
| 115 | [C_STATE_C7_SHORT_LAT] = { |
| 116 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 117 | .power = 700, |
| 118 | .resource = MWAIT_RES(3, 0), |
| 119 | }, |
| 120 | [C_STATE_C7_LONG_LAT] = { |
| 121 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 122 | .power = 700, |
| 123 | .resource = MWAIT_RES(3, 1), |
| 124 | }, |
| 125 | [C_STATE_C7S_SHORT_LAT] = { |
| 126 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 127 | .power = 700, |
| 128 | .resource = MWAIT_RES(3, 2), |
| 129 | }, |
| 130 | [C_STATE_C7S_LONG_LAT] = { |
| 131 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 132 | .power = 700, |
| 133 | .resource = MWAIT_RES(3, 3), |
| 134 | }, |
| 135 | [C_STATE_C8] = { |
| 136 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
| 137 | .power = 600, |
| 138 | .resource = MWAIT_RES(4, 0), |
| 139 | }, |
| 140 | [C_STATE_C9] = { |
| 141 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
| 142 | .power = 500, |
| 143 | .resource = MWAIT_RES(5, 0), |
| 144 | }, |
| 145 | [C_STATE_C10] = { |
| 146 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
| 147 | .power = 400, |
| 148 | .resource = MWAIT_RES(6, 0), |
| 149 | }, |
| 150 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 151 | |
| 152 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 153 | static const u8 power_limit_time_sec_to_msr[] = { |
| 154 | [0] = 0x00, |
| 155 | [1] = 0x0a, |
| 156 | [2] = 0x0b, |
| 157 | [3] = 0x4b, |
| 158 | [4] = 0x0c, |
| 159 | [5] = 0x2c, |
| 160 | [6] = 0x4c, |
| 161 | [7] = 0x6c, |
| 162 | [8] = 0x0d, |
| 163 | [10] = 0x2d, |
| 164 | [12] = 0x4d, |
| 165 | [14] = 0x6d, |
| 166 | [16] = 0x0e, |
| 167 | [20] = 0x2e, |
| 168 | [24] = 0x4e, |
| 169 | [28] = 0x6e, |
| 170 | [32] = 0x0f, |
| 171 | [40] = 0x2f, |
| 172 | [48] = 0x4f, |
| 173 | [56] = 0x6f, |
| 174 | [64] = 0x10, |
| 175 | [80] = 0x30, |
| 176 | [96] = 0x50, |
| 177 | [112] = 0x70, |
| 178 | [128] = 0x11, |
| 179 | }; |
| 180 | |
| 181 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 182 | static const u8 power_limit_time_msr_to_sec[] = { |
| 183 | [0x00] = 0, |
| 184 | [0x0a] = 1, |
| 185 | [0x0b] = 2, |
| 186 | [0x4b] = 3, |
| 187 | [0x0c] = 4, |
| 188 | [0x2c] = 5, |
| 189 | [0x4c] = 6, |
| 190 | [0x6c] = 7, |
| 191 | [0x0d] = 8, |
| 192 | [0x2d] = 10, |
| 193 | [0x4d] = 12, |
| 194 | [0x6d] = 14, |
| 195 | [0x0e] = 16, |
| 196 | [0x2e] = 20, |
| 197 | [0x4e] = 24, |
| 198 | [0x6e] = 28, |
| 199 | [0x0f] = 32, |
| 200 | [0x2f] = 40, |
| 201 | [0x4f] = 48, |
| 202 | [0x6f] = 56, |
| 203 | [0x10] = 64, |
| 204 | [0x30] = 80, |
| 205 | [0x50] = 96, |
| 206 | [0x70] = 112, |
| 207 | [0x11] = 128, |
| 208 | }; |
| 209 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 210 | /* Dynamically determine if the part is ULT. */ |
| 211 | static int is_ult(void) |
| 212 | { |
| 213 | static int ult = -1; |
| 214 | |
| 215 | if (ult < 0) |
| 216 | ult = (cpuid_eax(1) > 0x40650); |
| 217 | |
| 218 | return ult; |
| 219 | } |
| 220 | |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 221 | /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate |
| 222 | * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly |
| 223 | * when a core is woken up. */ |
| 224 | static int pcode_ready(void) |
| 225 | { |
| 226 | int wait_count; |
| 227 | const int delay_step = 10; |
| 228 | |
| 229 | wait_count = 0; |
| 230 | do { |
| 231 | if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) |
| 232 | return 0; |
| 233 | wait_count += delay_step; |
| 234 | udelay(delay_step); |
| 235 | } while (wait_count < 1000); |
| 236 | |
| 237 | return -1; |
| 238 | } |
| 239 | |
| 240 | static void calibrate_24mhz_bclk(void) |
| 241 | { |
| 242 | int err_code; |
| 243 | |
| 244 | if (pcode_ready() < 0) { |
| 245 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 246 | return; |
| 247 | } |
| 248 | |
| 249 | /* A non-zero value initiates the PCODE calibration. */ |
| 250 | MCHBAR32(BIOS_MAILBOX_DATA) = ~0; |
| 251 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| 252 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; |
| 253 | |
| 254 | if (pcode_ready() < 0) { |
| 255 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 256 | return; |
| 257 | } |
| 258 | |
| 259 | err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; |
| 260 | |
| 261 | printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", |
| 262 | err_code); |
| 263 | |
| 264 | /* Read the calibrated value. */ |
| 265 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| 266 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; |
| 267 | |
| 268 | if (pcode_ready() < 0) { |
| 269 | printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); |
| 270 | return; |
| 271 | } |
| 272 | |
| 273 | printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", |
| 274 | MCHBAR32(BIOS_MAILBOX_DATA)); |
| 275 | } |
| 276 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame^] | 277 | static u32 pcode_mailbox_read(u32 command) |
| 278 | { |
| 279 | if (pcode_ready() < 0) { |
| 280 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 281 | return 0; |
| 282 | } |
| 283 | |
| 284 | /* Send command and start transaction */ |
| 285 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; |
| 286 | |
| 287 | if (pcode_ready() < 0) { |
| 288 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | /* Read mailbox */ |
| 293 | return MCHBAR32(BIOS_MAILBOX_DATA); |
| 294 | } |
| 295 | |
| 296 | static void configure_pch_power_sharing(void) |
| 297 | { |
| 298 | u32 pch_power, pch_power_ext, pmsync, pmsync2; |
| 299 | int i; |
| 300 | |
| 301 | /* Read PCH Power levels from PCODE */ |
| 302 | pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); |
| 303 | pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); |
| 304 | |
| 305 | printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", |
| 306 | pch_power, pch_power_ext); |
| 307 | |
| 308 | pmsync = RCBA32(PMSYNC_CONFIG); |
| 309 | pmsync2 = RCBA32(PMSYNC_CONFIG2); |
| 310 | |
| 311 | /* Program PMSYNC_TPR_CONFIG PCH power limit values |
| 312 | * pmsync[0:4] = mailbox[0:5] |
| 313 | * pmsync[8:12] = mailbox[6:11] |
| 314 | * pmsync[16:20] = mailbox[12:17] |
| 315 | */ |
| 316 | for (i = 0; i < 3; i++) { |
| 317 | u32 level = pch_power & 0x3f; |
| 318 | pch_power >>= 6; |
| 319 | pmsync &= ~(0x1f << (i * 8)); |
| 320 | pmsync |= (level & 0x1f) << (i * 8); |
| 321 | } |
| 322 | RCBA32(PMSYNC_CONFIG) = pmsync; |
| 323 | |
| 324 | /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values |
| 325 | * pmsync2[0:4] = mailbox[23:18] |
| 326 | * pmsync2[8:12] = mailbox_ext[6:11] |
| 327 | * pmsync2[16:20] = mailbox_ext[12:17] |
| 328 | * pmsync2[24:28] = mailbox_ext[18:22] |
| 329 | */ |
| 330 | pmsync2 &= ~0x1f; |
| 331 | pmsync2 |= pch_power & 0x1f; |
| 332 | |
| 333 | for (i = 1; i < 4; i++) { |
| 334 | u32 level = pch_power_ext & 0x3f; |
| 335 | pch_power_ext >>= 6; |
| 336 | pmsync2 &= ~(0x1f << (i * 8)); |
| 337 | pmsync2 |= (level & 0x1f) << (i * 8); |
| 338 | } |
| 339 | RCBA32(PMSYNC_CONFIG2) = pmsync2; |
| 340 | } |
| 341 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 342 | int cpu_config_tdp_levels(void) |
| 343 | { |
| 344 | msr_t platform_info; |
| 345 | |
| 346 | /* Bits 34:33 indicate how many levels supported */ |
| 347 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 348 | return (platform_info.hi >> 1) & 3; |
| 349 | } |
| 350 | |
| 351 | /* |
| 352 | * Configure processor power limits if possible |
| 353 | * This must be done AFTER set of BIOS_RESET_CPL |
| 354 | */ |
| 355 | void set_power_limits(u8 power_limit_1_time) |
| 356 | { |
| 357 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 358 | msr_t limit; |
| 359 | unsigned power_unit; |
| 360 | unsigned tdp, min_power, max_power, max_time; |
| 361 | u8 power_limit_1_val; |
| 362 | |
| 363 | if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) |
| 364 | return; |
| 365 | |
| 366 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 367 | return; |
| 368 | |
| 369 | /* Get units */ |
| 370 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 371 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 372 | |
| 373 | /* Get power defaults for this SKU */ |
| 374 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 375 | tdp = msr.lo & 0x7fff; |
| 376 | min_power = (msr.lo >> 16) & 0x7fff; |
| 377 | max_power = msr.hi & 0x7fff; |
| 378 | max_time = (msr.hi >> 16) & 0x7f; |
| 379 | |
| 380 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 381 | |
| 382 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 383 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 384 | |
| 385 | if (min_power > 0 && tdp < min_power) |
| 386 | tdp = min_power; |
| 387 | |
| 388 | if (max_power > 0 && tdp > max_power) |
| 389 | tdp = max_power; |
| 390 | |
| 391 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 392 | |
| 393 | /* Set long term power limit to TDP */ |
| 394 | limit.lo = 0; |
| 395 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 396 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 397 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 398 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 399 | |
| 400 | /* Set short term power limit to 1.25 * TDP */ |
| 401 | limit.hi = 0; |
| 402 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 403 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 404 | /* Power limit 2 time is only programmable on SNB EP/EX */ |
| 405 | |
| 406 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 407 | |
| 408 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 409 | if (cpu_config_tdp_levels()) { |
| 410 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 411 | limit.hi = 0; |
| 412 | limit.lo = msr.lo & 0xff; |
| 413 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 414 | } |
| 415 | } |
| 416 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 417 | static void configure_c_states(void) |
| 418 | { |
| 419 | msr_t msr; |
| 420 | |
| 421 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 422 | msr.lo |= (1 << 30); // Package c-state Undemotion Enable |
| 423 | msr.lo |= (1 << 29); // Package c-state Demotion Enable |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 424 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 425 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 426 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 427 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 428 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 429 | msr.lo &= ~(0xf); // Clear deepest package c-state |
| 430 | /* FIXME: The deepest package c-state is set to C0/C1 to work around |
| 431 | * platform instability when package C3 or deeper c-states are used. */ |
| 432 | msr.lo |= 0; // Deepeset package c-state is C0/C1. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 433 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
| 434 | |
| 435 | msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 436 | msr.lo &= ~0xffff; |
| 437 | msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address |
| 438 | /* The deepest package c-state defaults to factory-configured value. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 439 | wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); |
| 440 | |
| 441 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 442 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 443 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 444 | |
| 445 | msr = rdmsr(MSR_POWER_CTL); |
| 446 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 447 | msr.lo |= (1 << 1); // C1E Enable |
| 448 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 449 | wrmsr(MSR_POWER_CTL, msr); |
| 450 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 451 | /* C-state Interrupt Response Latency Control 0 - package C3 latency */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 452 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 453 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; |
| 454 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 455 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 456 | /* C-state Interrupt Response Latency Control 1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 457 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 458 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
| 459 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 460 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 461 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 462 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 463 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
| 464 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 465 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 466 | /* Haswell ULT only supoprts the 3-5 latency response registers.*/ |
| 467 | if (is_ult()) { |
| 468 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 469 | msr.hi = 0; |
| 470 | msr.lo = IRTL_VALID | IRTL_1024_NS | |
| 471 | C_STATE_LATENCY_CONTROL_3_LIMIT; |
| 472 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 473 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 474 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 475 | msr.hi = 0; |
| 476 | msr.lo = IRTL_VALID | IRTL_1024_NS | |
| 477 | C_STATE_LATENCY_CONTROL_4_LIMIT; |
| 478 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 479 | |
| 480 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 481 | msr.hi = 0; |
| 482 | msr.lo = IRTL_VALID | IRTL_1024_NS | |
| 483 | C_STATE_LATENCY_CONTROL_5_LIMIT; |
| 484 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| 485 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 486 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 487 | |
| 488 | static void configure_thermal_target(void) |
| 489 | { |
| 490 | struct cpu_intel_haswell_config *conf; |
| 491 | device_t lapic; |
| 492 | msr_t msr; |
| 493 | |
| 494 | /* Find pointer to CPU configuration */ |
| 495 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 496 | if (!lapic || !lapic->chip_info) |
| 497 | return; |
| 498 | conf = lapic->chip_info; |
| 499 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 500 | /* Set TCC activation offset if supported */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 501 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 502 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 503 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 504 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 505 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 506 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | static void configure_misc(void) |
| 511 | { |
| 512 | msr_t msr; |
| 513 | |
| 514 | msr = rdmsr(IA32_MISC_ENABLE); |
| 515 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 516 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 517 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 518 | wrmsr(IA32_MISC_ENABLE, msr); |
| 519 | |
| 520 | /* Disable Thermal interrupts */ |
| 521 | msr.lo = 0; |
| 522 | msr.hi = 0; |
| 523 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 524 | |
| 525 | /* Enable package critical interrupt only */ |
| 526 | msr.lo = 1 << 4; |
| 527 | msr.hi = 0; |
| 528 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 529 | } |
| 530 | |
| 531 | static void enable_lapic_tpr(void) |
| 532 | { |
| 533 | msr_t msr; |
| 534 | |
| 535 | msr = rdmsr(MSR_PIC_MSG_CONTROL); |
| 536 | msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ |
| 537 | wrmsr(MSR_PIC_MSG_CONTROL, msr); |
| 538 | } |
| 539 | |
| 540 | static void configure_dca_cap(void) |
| 541 | { |
| 542 | struct cpuid_result cpuid_regs; |
| 543 | msr_t msr; |
| 544 | |
| 545 | /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ |
| 546 | cpuid_regs = cpuid(1); |
| 547 | if (cpuid_regs.ecx & (1 << 18)) { |
| 548 | msr = rdmsr(IA32_PLATFORM_DCA_CAP); |
| 549 | msr.lo |= 1; |
| 550 | wrmsr(IA32_PLATFORM_DCA_CAP, msr); |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | static void set_max_ratio(void) |
| 555 | { |
| 556 | msr_t msr, perf_ctl; |
| 557 | |
| 558 | perf_ctl.hi = 0; |
| 559 | |
| 560 | /* Check for configurable TDP option */ |
| 561 | if (cpu_config_tdp_levels()) { |
| 562 | /* Set to nominal TDP ratio */ |
| 563 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 564 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 565 | } else { |
| 566 | /* Platform Info bits 15:8 give max ratio */ |
| 567 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 568 | perf_ctl.lo = msr.lo & 0xff00; |
| 569 | } |
| 570 | wrmsr(IA32_PERF_CTL, perf_ctl); |
| 571 | |
| 572 | printk(BIOS_DEBUG, "haswell: frequency set to %d\n", |
| 573 | ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); |
| 574 | } |
| 575 | |
| 576 | static void set_energy_perf_bias(u8 policy) |
| 577 | { |
| 578 | msr_t msr; |
Aaron Durbin | dc278f8 | 2012-12-11 17:15:13 -0600 | [diff] [blame] | 579 | int ecx; |
| 580 | |
| 581 | /* Determine if energy efficient policy is supported. */ |
| 582 | ecx = cpuid_ecx(0x6); |
| 583 | if (!(ecx & (1 << 3))) |
| 584 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 585 | |
| 586 | /* Energy Policy is bits 3:0 */ |
| 587 | msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); |
| 588 | msr.lo &= ~0xf; |
| 589 | msr.lo |= policy & 0xf; |
| 590 | wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); |
| 591 | |
| 592 | printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", |
| 593 | policy); |
| 594 | } |
| 595 | |
| 596 | static void configure_mca(void) |
| 597 | { |
| 598 | msr_t msr; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 599 | const unsigned int mcg_cap_msr = 0x179; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 600 | int i; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 601 | int num_banks; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 602 | |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 603 | msr = rdmsr(mcg_cap_msr); |
| 604 | num_banks = msr.lo & 0xff; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 605 | msr.lo = msr.hi = 0; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 606 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 607 | * of these banks are core vs package scope. For now every CPU clears |
| 608 | * every bank. */ |
| 609 | for (i = 0; i < num_banks; i++) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 610 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| 611 | } |
| 612 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 613 | static void bsp_init_before_ap_bringup(struct bus *cpu_bus) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 614 | { |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 615 | struct device_path cpu_path; |
| 616 | struct cpu_info *info; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 617 | char processor_name[49]; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 618 | |
| 619 | /* Print processor name */ |
| 620 | fill_processor_name(processor_name); |
| 621 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
| 622 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 623 | /* Ensure the local apic is enabled */ |
| 624 | enable_lapic(); |
| 625 | |
| 626 | /* Set the device path of the boot cpu. */ |
| 627 | cpu_path.type = DEVICE_PATH_APIC; |
| 628 | cpu_path.apic.apic_id = lapicid(); |
| 629 | |
| 630 | /* Find the device structure for the boot cpu. */ |
| 631 | info = cpu_info(); |
| 632 | info->cpu = alloc_find_dev(cpu_bus, &cpu_path); |
| 633 | |
| 634 | if (info->index != 0) |
| 635 | printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); |
| 636 | |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 637 | /* Setup MTRRs based on physical address size. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 638 | x86_setup_fixed_mtrrs(); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 639 | x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 640 | x86_mtrr_check(); |
| 641 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame^] | 642 | if (is_ult()) { |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 643 | calibrate_24mhz_bclk(); |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame^] | 644 | configure_pch_power_sharing(); |
| 645 | } |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 646 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 647 | /* Call through the cpu driver's initialization. */ |
| 648 | cpu_initialize(0); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 649 | } |
| 650 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 651 | /* All CPUs including BSP will run the following function. */ |
| 652 | static void haswell_init(device_t cpu) |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 653 | { |
| 654 | /* Clear out pending MCEs */ |
| 655 | configure_mca(); |
| 656 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 657 | /* Enable the local cpu apics */ |
| 658 | enable_lapic_tpr(); |
| 659 | setup_lapic(); |
| 660 | |
| 661 | /* Configure C States */ |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 662 | configure_c_states(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 663 | |
| 664 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 665 | configure_misc(); |
| 666 | |
| 667 | /* Thermal throttle activation offset */ |
| 668 | configure_thermal_target(); |
| 669 | |
| 670 | /* Enable Direct Cache Access */ |
| 671 | configure_dca_cap(); |
| 672 | |
| 673 | /* Set energy policy */ |
| 674 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 675 | |
| 676 | /* Set Max Ratio */ |
| 677 | set_max_ratio(); |
| 678 | |
| 679 | /* Enable Turbo */ |
| 680 | enable_turbo(); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 681 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 682 | |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 683 | void bsp_init_and_start_aps(struct bus *cpu_bus) |
| 684 | { |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 685 | int max_cpus; |
| 686 | int num_aps; |
| 687 | const void *microcode_patch; |
| 688 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 689 | /* Perform any necessary BSP initialization before APs are brought up. |
| 690 | * This call also allows the BSP to prepare for any secondary effects |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 691 | * from calling cpu_initialize() such as smm_init(). */ |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 692 | bsp_init_before_ap_bringup(cpu_bus); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 693 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 694 | microcode_patch = intel_microcode_find(); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 695 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 696 | /* This needs to be called after the mtrr setup so the BSP mtrrs |
| 697 | * can be mirrored by the APs. */ |
| 698 | if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) { |
| 699 | printk(BIOS_CRIT, "AP setup initialization failed. " |
| 700 | "No APs will be brought up.\n"); |
| 701 | return; |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 702 | } |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 703 | |
| 704 | num_aps = max_cpus - 1; |
| 705 | if (start_aps(cpu_bus, num_aps)) { |
| 706 | printk(BIOS_CRIT, "AP startup failed. Trying to continue.\n"); |
| 707 | } |
| 708 | |
| 709 | if (smm_initialize()) { |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 710 | printk(BIOS_CRIT, "SMM Initialization failed...\n"); |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 711 | return; |
| 712 | } |
| 713 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 714 | /* After SMM relocation a 2nd microcode load is required. */ |
| 715 | intel_microcode_load_unlocked(microcode_patch); |
Aaron Durbin | 23f5016 | 2013-04-03 09:55:22 -0500 | [diff] [blame] | 716 | |
| 717 | /* Enable ROM caching if option was selected. */ |
| 718 | x86_mtrr_enable_rom_caching(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 719 | } |
| 720 | |
| 721 | static struct device_operations cpu_dev_ops = { |
| 722 | .init = haswell_init, |
| 723 | }; |
| 724 | |
| 725 | static struct cpu_device_id cpu_table[] = { |
| 726 | { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ |
| 727 | { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ |
Duncan Laurie | 51254049 | 2012-12-17 11:24:45 -0800 | [diff] [blame] | 728 | { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ |
| 729 | { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 730 | { 0, 0 }, |
| 731 | }; |
| 732 | |
| 733 | static const struct cpu_driver driver __cpu_driver = { |
| 734 | .ops = &cpu_dev_ops, |
| 735 | .id_table = cpu_table, |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 736 | .cstates = cstate_map, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 737 | }; |
| 738 | |