commit 7b5f12b9b2695359b6ccb4d62bdb868166c7f8d1
author Lee Leahy <leroy.p.leahy@intel.com> Wed Mar 15 17:16:59 2017 -0700
committer Lee Leahy <leroy.p.leahy@intel.com> Thu Mar 16 04:13:06 2017 +0100
tree 6b04150aa316965fd472b3dc127c374df6b34469
parent dfc8a560d7fec715a652f428dc3cab3e0a92c680

cpu/intel: Indent with tabs

Fix the following error and warning detected by checkpatch.pl:

ERROR: code indent should use tabs where possible
WARNING: please, no space before tabs

TEST=Build and run on Galileo Gen2

Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/cpu/intel/haswell/haswell_init.c

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 0b243ad..d7ff121 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -50,7 +50,7 @@
 	(((1 << ((base)*5)) * (limit)) / 1000)
 #define C_STATE_LATENCY_FROM_LAT_REG(reg) \
 	C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
-	                              (IRTL_1024_NS >> 10))
+				      (IRTL_1024_NS >> 10))
 
 /*
  * List of supported C-states in this processor. Only the ULT parts support C8,
@@ -361,7 +361,7 @@
 	pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
 
 	printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
-               pch_power, pch_power_ext);
+		pch_power, pch_power_ext);
 
 	pmsync = RCBA32(PMSYNC_CONFIG);
 	pmsync2 = RCBA32(PMSYNC_CONFIG2);
@@ -532,19 +532,19 @@
 		/* C-state Interrupt Response Latency Control 3 - package C8 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
-		         C_STATE_LATENCY_CONTROL_3_LIMIT;
+			 C_STATE_LATENCY_CONTROL_3_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
 
 		/* C-state Interrupt Response Latency Control 4 - package C9 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
-		         C_STATE_LATENCY_CONTROL_4_LIMIT;
+			 C_STATE_LATENCY_CONTROL_4_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
 
 		/* C-state Interrupt Response Latency Control 5 - package C10 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
-		         C_STATE_LATENCY_CONTROL_5_LIMIT;
+			 C_STATE_LATENCY_CONTROL_5_LIMIT;
 		wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 	}
 }
@@ -577,7 +577,7 @@
 
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	  /* Fast String enable */
-	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
 	wrmsr(IA32_MISC_ENABLE, msr);