Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | #include <string.h> |
| 21 | #include <arch/acpi.h> |
| 22 | #include <cpu/cpu.h> |
| 23 | #include <cpu/x86/mtrr.h> |
| 24 | #include <cpu/x86/msr.h> |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 25 | #include <cpu/x86/mp.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | #include <cpu/x86/lapic.h> |
| 27 | #include <cpu/intel/microcode.h> |
| 28 | #include <cpu/intel/speedstep.h> |
| 29 | #include <cpu/intel/turbo.h> |
| 30 | #include <cpu/x86/cache.h> |
| 31 | #include <cpu/x86/name.h> |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 32 | #include <cpu/x86/smm.h> |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 33 | #include <delay.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | #include <pc80/mc146818rtc.h> |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 35 | #include <northbridge/intel/haswell/haswell.h> |
| 36 | #include <southbridge/intel/lynxpoint/pch.h> |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 37 | #include <cpu/intel/common/common.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | #include "haswell.h" |
| 39 | #include "chip.h" |
| 40 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 41 | /* Intel suggested latency times in units of 1024ns. */ |
| 42 | #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 |
| 43 | #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 |
| 44 | #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 |
| 45 | #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 |
| 46 | #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 |
| 47 | #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef |
| 48 | |
| 49 | #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ |
| 50 | (((1 << ((base)*5)) * (limit)) / 1000) |
| 51 | #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ |
| 52 | C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 53 | (IRTL_1024_NS >> 10)) |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 54 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 55 | /* |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 56 | * List of supported C-states in this processor. Only the ULT parts support C8, |
| 57 | * C9, and C10. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | */ |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 59 | enum { |
| 60 | C_STATE_C0, /* 0 */ |
| 61 | C_STATE_C1, /* 1 */ |
| 62 | C_STATE_C1E, /* 2 */ |
| 63 | C_STATE_C3, /* 3 */ |
| 64 | C_STATE_C6_SHORT_LAT, /* 4 */ |
| 65 | C_STATE_C6_LONG_LAT, /* 5 */ |
| 66 | C_STATE_C7_SHORT_LAT, /* 6 */ |
| 67 | C_STATE_C7_LONG_LAT, /* 7 */ |
| 68 | C_STATE_C7S_SHORT_LAT, /* 8 */ |
| 69 | C_STATE_C7S_LONG_LAT, /* 9 */ |
| 70 | C_STATE_C8, /* 10 */ |
| 71 | C_STATE_C9, /* 11 */ |
| 72 | C_STATE_C10, /* 12 */ |
| 73 | NUM_C_STATES |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | }; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 75 | |
| 76 | #define MWAIT_RES(state, sub_state) \ |
| 77 | { \ |
| 78 | .addrl = (((state) << 4) | (sub_state)), \ |
| 79 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 80 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 81 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 82 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 83 | } |
| 84 | |
| 85 | static acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 86 | [C_STATE_C0] = { }, |
| 87 | [C_STATE_C1] = { |
| 88 | .latency = 0, |
| 89 | .power = 1000, |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 90 | .resource = MWAIT_RES(0, 0), |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 91 | }, |
| 92 | [C_STATE_C1E] = { |
| 93 | .latency = 0, |
| 94 | .power = 1000, |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 95 | .resource = MWAIT_RES(0, 1), |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 96 | }, |
| 97 | [C_STATE_C3] = { |
| 98 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 99 | .power = 900, |
| 100 | .resource = MWAIT_RES(1, 0), |
| 101 | }, |
| 102 | [C_STATE_C6_SHORT_LAT] = { |
| 103 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 104 | .power = 800, |
| 105 | .resource = MWAIT_RES(2, 0), |
| 106 | }, |
| 107 | [C_STATE_C6_LONG_LAT] = { |
| 108 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 109 | .power = 800, |
| 110 | .resource = MWAIT_RES(2, 1), |
| 111 | }, |
| 112 | [C_STATE_C7_SHORT_LAT] = { |
| 113 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 114 | .power = 700, |
| 115 | .resource = MWAIT_RES(3, 0), |
| 116 | }, |
| 117 | [C_STATE_C7_LONG_LAT] = { |
| 118 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 119 | .power = 700, |
| 120 | .resource = MWAIT_RES(3, 1), |
| 121 | }, |
| 122 | [C_STATE_C7S_SHORT_LAT] = { |
| 123 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 124 | .power = 700, |
| 125 | .resource = MWAIT_RES(3, 2), |
| 126 | }, |
| 127 | [C_STATE_C7S_LONG_LAT] = { |
| 128 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 129 | .power = 700, |
| 130 | .resource = MWAIT_RES(3, 3), |
| 131 | }, |
| 132 | [C_STATE_C8] = { |
| 133 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
| 134 | .power = 600, |
| 135 | .resource = MWAIT_RES(4, 0), |
| 136 | }, |
| 137 | [C_STATE_C9] = { |
| 138 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
| 139 | .power = 500, |
| 140 | .resource = MWAIT_RES(5, 0), |
| 141 | }, |
| 142 | [C_STATE_C10] = { |
| 143 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
| 144 | .power = 400, |
| 145 | .resource = MWAIT_RES(6, 0), |
| 146 | }, |
| 147 | }; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | |
| 149 | /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ |
| 150 | static const u8 power_limit_time_sec_to_msr[] = { |
| 151 | [0] = 0x00, |
| 152 | [1] = 0x0a, |
| 153 | [2] = 0x0b, |
| 154 | [3] = 0x4b, |
| 155 | [4] = 0x0c, |
| 156 | [5] = 0x2c, |
| 157 | [6] = 0x4c, |
| 158 | [7] = 0x6c, |
| 159 | [8] = 0x0d, |
| 160 | [10] = 0x2d, |
| 161 | [12] = 0x4d, |
| 162 | [14] = 0x6d, |
| 163 | [16] = 0x0e, |
| 164 | [20] = 0x2e, |
| 165 | [24] = 0x4e, |
| 166 | [28] = 0x6e, |
| 167 | [32] = 0x0f, |
| 168 | [40] = 0x2f, |
| 169 | [48] = 0x4f, |
| 170 | [56] = 0x6f, |
| 171 | [64] = 0x10, |
| 172 | [80] = 0x30, |
| 173 | [96] = 0x50, |
| 174 | [112] = 0x70, |
| 175 | [128] = 0x11, |
| 176 | }; |
| 177 | |
| 178 | /* Convert POWER_LIMIT_1_TIME MSR value to seconds */ |
| 179 | static const u8 power_limit_time_msr_to_sec[] = { |
| 180 | [0x00] = 0, |
| 181 | [0x0a] = 1, |
| 182 | [0x0b] = 2, |
| 183 | [0x4b] = 3, |
| 184 | [0x0c] = 4, |
| 185 | [0x2c] = 5, |
| 186 | [0x4c] = 6, |
| 187 | [0x6c] = 7, |
| 188 | [0x0d] = 8, |
| 189 | [0x2d] = 10, |
| 190 | [0x4d] = 12, |
| 191 | [0x6d] = 14, |
| 192 | [0x0e] = 16, |
| 193 | [0x2e] = 20, |
| 194 | [0x4e] = 24, |
| 195 | [0x6e] = 28, |
| 196 | [0x0f] = 32, |
| 197 | [0x2f] = 40, |
| 198 | [0x4f] = 48, |
| 199 | [0x6f] = 56, |
| 200 | [0x10] = 64, |
| 201 | [0x30] = 80, |
| 202 | [0x50] = 96, |
| 203 | [0x70] = 112, |
| 204 | [0x11] = 128, |
| 205 | }; |
| 206 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 207 | int haswell_family_model(void) |
| 208 | { |
| 209 | return cpuid_eax(1) & 0x0fff0ff0; |
| 210 | } |
| 211 | |
| 212 | int haswell_stepping(void) |
| 213 | { |
| 214 | return cpuid_eax(1) & 0xf; |
| 215 | } |
| 216 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 217 | /* Dynamically determine if the part is ULT. */ |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 218 | int haswell_is_ult(void) |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 219 | { |
| 220 | static int ult = -1; |
| 221 | |
| 222 | if (ult < 0) |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 223 | ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 224 | |
| 225 | return ult; |
| 226 | } |
| 227 | |
Aaron Durbin | f24262d | 2013-04-10 14:59:21 -0500 | [diff] [blame] | 228 | /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate |
| 229 | * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly |
| 230 | * when a core is woken up. */ |
| 231 | static int pcode_ready(void) |
| 232 | { |
| 233 | int wait_count; |
| 234 | const int delay_step = 10; |
| 235 | |
| 236 | wait_count = 0; |
| 237 | do { |
| 238 | if (!(MCHBAR32(BIOS_MAILBOX_INTERFACE) & MAILBOX_RUN_BUSY)) |
| 239 | return 0; |
| 240 | wait_count += delay_step; |
| 241 | udelay(delay_step); |
| 242 | } while (wait_count < 1000); |
| 243 | |
| 244 | return -1; |
| 245 | } |
| 246 | |
| 247 | static void calibrate_24mhz_bclk(void) |
| 248 | { |
| 249 | int err_code; |
| 250 | |
| 251 | if (pcode_ready() < 0) { |
| 252 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 253 | return; |
| 254 | } |
| 255 | |
| 256 | /* A non-zero value initiates the PCODE calibration. */ |
| 257 | MCHBAR32(BIOS_MAILBOX_DATA) = ~0; |
| 258 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| 259 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL; |
| 260 | |
| 261 | if (pcode_ready() < 0) { |
| 262 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 263 | return; |
| 264 | } |
| 265 | |
| 266 | err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; |
| 267 | |
| 268 | printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", |
| 269 | err_code); |
| 270 | |
| 271 | /* Read the calibrated value. */ |
| 272 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = |
| 273 | MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION; |
| 274 | |
| 275 | if (pcode_ready() < 0) { |
| 276 | printk(BIOS_ERR, "PCODE: mailbox timeout on read.\n"); |
| 277 | return; |
| 278 | } |
| 279 | |
| 280 | printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", |
| 281 | MCHBAR32(BIOS_MAILBOX_DATA)); |
| 282 | } |
| 283 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 284 | static u32 pcode_mailbox_read(u32 command) |
| 285 | { |
| 286 | if (pcode_ready() < 0) { |
| 287 | printk(BIOS_ERR, "PCODE: mailbox timeout on wait ready.\n"); |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | /* Send command and start transaction */ |
| 292 | MCHBAR32(BIOS_MAILBOX_INTERFACE) = command | MAILBOX_RUN_BUSY; |
| 293 | |
| 294 | if (pcode_ready() < 0) { |
| 295 | printk(BIOS_ERR, "PCODE: mailbox timeout on completion.\n"); |
| 296 | return 0; |
| 297 | } |
| 298 | |
| 299 | /* Read mailbox */ |
| 300 | return MCHBAR32(BIOS_MAILBOX_DATA); |
| 301 | } |
| 302 | |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 303 | static void initialize_vr_config(void) |
| 304 | { |
| 305 | msr_t msr; |
| 306 | |
| 307 | printk(BIOS_DEBUG, "Initializing VR config.\n"); |
| 308 | |
| 309 | /* Configure VR_CURRENT_CONFIG. */ |
| 310 | msr = rdmsr(MSR_VR_CURRENT_CONFIG); |
| 311 | /* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid |
| 312 | * on ULT systems. */ |
| 313 | msr.hi &= 0xc0000000; |
| 314 | msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ |
| 315 | msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ |
| 316 | msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ |
| 317 | |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 318 | if (haswell_is_ult()) |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 319 | msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ |
| 320 | /* Leave the max instantaneous current limit (12:0) to default. */ |
| 321 | wrmsr(MSR_VR_CURRENT_CONFIG, msr); |
| 322 | |
| 323 | /* Configure VR_MISC_CONFIG MSR. */ |
| 324 | msr = rdmsr(MSR_VR_MISC_CONFIG); |
| 325 | /* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format. */ |
| 326 | msr.hi &= ~(0x3ff << (40 - 32)); |
| 327 | msr.hi |= (0x200 << (40 - 32)); /* 1.0 */ |
| 328 | /* Set IOUT_OFFSET to 0. */ |
| 329 | msr.hi &= ~0xff; |
| 330 | /* Set exit ramp rate to fast. */ |
| 331 | msr.hi |= (1 << (50 - 32)); |
| 332 | /* Set entry ramp rate to slow. */ |
| 333 | msr.hi &= ~(1 << (51 - 32)); |
| 334 | /* Enable decay mode on C-state entry. */ |
| 335 | msr.hi |= (1 << (52 - 32)); |
| 336 | /* Set the slow ramp rate to be fast ramp rate / 4 */ |
| 337 | msr.hi &= ~(0x3 << (53 - 32)); |
| 338 | msr.hi |= (0x01 << (53 - 32)); |
| 339 | /* Set MIN_VID (31:24) to allow CPU to have full control. */ |
| 340 | msr.lo &= ~0xff000000; |
| 341 | wrmsr(MSR_VR_MISC_CONFIG, msr); |
| 342 | |
| 343 | /* Configure VR_MISC_CONFIG2 MSR. */ |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 344 | if (haswell_is_ult()) { |
Aaron Durbin | 16cbf89 | 2013-07-03 16:21:28 -0500 | [diff] [blame] | 345 | msr = rdmsr(MSR_VR_MISC_CONFIG2); |
| 346 | msr.lo &= ~0xffff; |
| 347 | /* Allow CPU to control minimum voltage completely (15:8) and |
| 348 | * set the fast ramp voltage to 1110mV (0x6f in 10mV steps). */ |
| 349 | msr.lo |= 0x006f; |
| 350 | wrmsr(MSR_VR_MISC_CONFIG2, msr); |
| 351 | } |
| 352 | } |
| 353 | |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 354 | static void configure_pch_power_sharing(void) |
| 355 | { |
| 356 | u32 pch_power, pch_power_ext, pmsync, pmsync2; |
| 357 | int i; |
| 358 | |
| 359 | /* Read PCH Power levels from PCODE */ |
| 360 | pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER); |
| 361 | pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT); |
| 362 | |
| 363 | printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 364 | pch_power, pch_power_ext); |
Duncan Laurie | e1e87e0 | 2013-04-26 10:35:19 -0700 | [diff] [blame] | 365 | |
| 366 | pmsync = RCBA32(PMSYNC_CONFIG); |
| 367 | pmsync2 = RCBA32(PMSYNC_CONFIG2); |
| 368 | |
| 369 | /* Program PMSYNC_TPR_CONFIG PCH power limit values |
| 370 | * pmsync[0:4] = mailbox[0:5] |
| 371 | * pmsync[8:12] = mailbox[6:11] |
| 372 | * pmsync[16:20] = mailbox[12:17] |
| 373 | */ |
| 374 | for (i = 0; i < 3; i++) { |
| 375 | u32 level = pch_power & 0x3f; |
| 376 | pch_power >>= 6; |
| 377 | pmsync &= ~(0x1f << (i * 8)); |
| 378 | pmsync |= (level & 0x1f) << (i * 8); |
| 379 | } |
| 380 | RCBA32(PMSYNC_CONFIG) = pmsync; |
| 381 | |
| 382 | /* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values |
| 383 | * pmsync2[0:4] = mailbox[23:18] |
| 384 | * pmsync2[8:12] = mailbox_ext[6:11] |
| 385 | * pmsync2[16:20] = mailbox_ext[12:17] |
| 386 | * pmsync2[24:28] = mailbox_ext[18:22] |
| 387 | */ |
| 388 | pmsync2 &= ~0x1f; |
| 389 | pmsync2 |= pch_power & 0x1f; |
| 390 | |
| 391 | for (i = 1; i < 4; i++) { |
| 392 | u32 level = pch_power_ext & 0x3f; |
| 393 | pch_power_ext >>= 6; |
| 394 | pmsync2 &= ~(0x1f << (i * 8)); |
| 395 | pmsync2 |= (level & 0x1f) << (i * 8); |
| 396 | } |
| 397 | RCBA32(PMSYNC_CONFIG2) = pmsync2; |
| 398 | } |
| 399 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 400 | int cpu_config_tdp_levels(void) |
| 401 | { |
| 402 | msr_t platform_info; |
| 403 | |
| 404 | /* Bits 34:33 indicate how many levels supported */ |
| 405 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 406 | return (platform_info.hi >> 1) & 3; |
| 407 | } |
| 408 | |
| 409 | /* |
| 410 | * Configure processor power limits if possible |
| 411 | * This must be done AFTER set of BIOS_RESET_CPL |
| 412 | */ |
| 413 | void set_power_limits(u8 power_limit_1_time) |
| 414 | { |
| 415 | msr_t msr = rdmsr(MSR_PLATFORM_INFO); |
| 416 | msr_t limit; |
Lee Leahy | 73a2894 | 2017-03-15 17:52:06 -0700 | [diff] [blame^] | 417 | unsigned int power_unit; |
| 418 | unsigned int tdp, min_power, max_power, max_time; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 419 | u8 power_limit_1_val; |
| 420 | |
Edward O'Callaghan | 5cfef13 | 2014-08-03 20:00:47 +1000 | [diff] [blame] | 421 | if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) |
| 422 | power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 423 | |
| 424 | if (!(msr.lo & PLATFORM_INFO_SET_TDP)) |
| 425 | return; |
| 426 | |
| 427 | /* Get units */ |
| 428 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 429 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 430 | |
| 431 | /* Get power defaults for this SKU */ |
| 432 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 433 | tdp = msr.lo & 0x7fff; |
| 434 | min_power = (msr.lo >> 16) & 0x7fff; |
| 435 | max_power = msr.hi & 0x7fff; |
| 436 | max_time = (msr.hi >> 16) & 0x7f; |
| 437 | |
| 438 | printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit); |
| 439 | |
| 440 | if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time) |
| 441 | power_limit_1_time = power_limit_time_msr_to_sec[max_time]; |
| 442 | |
| 443 | if (min_power > 0 && tdp < min_power) |
| 444 | tdp = min_power; |
| 445 | |
| 446 | if (max_power > 0 && tdp > max_power) |
| 447 | tdp = max_power; |
| 448 | |
| 449 | power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time]; |
| 450 | |
| 451 | /* Set long term power limit to TDP */ |
| 452 | limit.lo = 0; |
| 453 | limit.lo |= tdp & PKG_POWER_LIMIT_MASK; |
| 454 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 455 | limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << |
| 456 | PKG_POWER_LIMIT_TIME_SHIFT; |
| 457 | |
| 458 | /* Set short term power limit to 1.25 * TDP */ |
| 459 | limit.hi = 0; |
| 460 | limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; |
| 461 | limit.hi |= PKG_POWER_LIMIT_EN; |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 462 | /* Power limit 2 time is only programmable on server SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 463 | |
| 464 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 465 | |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 466 | /* Set power limit values in MCHBAR as well */ |
| 467 | MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; |
| 468 | MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; |
| 469 | |
| 470 | /* Set DDR RAPL power limit by copying from MMIO to MSR */ |
| 471 | msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); |
| 472 | msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); |
| 473 | wrmsr(MSR_DDR_RAPL_LIMIT, msr); |
| 474 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 475 | /* Use nominal TDP values for CPUs with configurable TDP */ |
| 476 | if (cpu_config_tdp_levels()) { |
| 477 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 478 | limit.hi = 0; |
| 479 | limit.lo = msr.lo & 0xff; |
| 480 | wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit); |
| 481 | } |
| 482 | } |
| 483 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 484 | static void configure_c_states(void) |
| 485 | { |
| 486 | msr_t msr; |
| 487 | |
| 488 | msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 489 | msr.lo |= (1 << 30); // Package c-state Undemotion Enable |
| 490 | msr.lo |= (1 << 29); // Package c-state Demotion Enable |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 491 | msr.lo |= (1 << 28); // C1 Auto Undemotion Enable |
| 492 | msr.lo |= (1 << 27); // C3 Auto Undemotion Enable |
| 493 | msr.lo |= (1 << 26); // C1 Auto Demotion Enable |
| 494 | msr.lo |= (1 << 25); // C3 Auto Demotion Enable |
| 495 | msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection |
Duncan Laurie | 1c09710 | 2013-05-07 13:19:56 -0700 | [diff] [blame] | 496 | /* The deepest package c-state defaults to factory-configured value. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 497 | wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); |
| 498 | |
| 499 | msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 500 | msr.lo &= ~0xffff; |
| 501 | msr.lo |= (get_pmbase() + 0x14); // LVL_2 base address |
| 502 | /* The deepest package c-state defaults to factory-configured value. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 503 | wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr); |
| 504 | |
| 505 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 506 | msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination |
| 507 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 508 | |
| 509 | msr = rdmsr(MSR_POWER_CTL); |
| 510 | msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 |
| 511 | msr.lo |= (1 << 1); // C1E Enable |
| 512 | msr.lo |= (1 << 0); // Bi-directional PROCHOT# |
| 513 | wrmsr(MSR_POWER_CTL, msr); |
| 514 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 515 | /* C-state Interrupt Response Latency Control 0 - package C3 latency */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 516 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 517 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; |
| 518 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 519 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 520 | /* C-state Interrupt Response Latency Control 1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 521 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 522 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; |
| 523 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 524 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 525 | /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 526 | msr.hi = 0; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 527 | msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; |
| 528 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 529 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 530 | /* Haswell ULT only supoprts the 3-5 latency response registers.*/ |
Duncan Laurie | 118d105 | 2013-07-09 15:34:25 -0700 | [diff] [blame] | 531 | if (haswell_is_ult()) { |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 532 | /* C-state Interrupt Response Latency Control 3 - package C8 */ |
| 533 | msr.hi = 0; |
| 534 | msr.lo = IRTL_VALID | IRTL_1024_NS | |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 535 | C_STATE_LATENCY_CONTROL_3_LIMIT; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 536 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 537 | |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 538 | /* C-state Interrupt Response Latency Control 4 - package C9 */ |
| 539 | msr.hi = 0; |
| 540 | msr.lo = IRTL_VALID | IRTL_1024_NS | |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 541 | C_STATE_LATENCY_CONTROL_4_LIMIT; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 542 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); |
| 543 | |
| 544 | /* C-state Interrupt Response Latency Control 5 - package C10 */ |
| 545 | msr.hi = 0; |
| 546 | msr.lo = IRTL_VALID | IRTL_1024_NS | |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 547 | C_STATE_LATENCY_CONTROL_5_LIMIT; |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 548 | wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); |
| 549 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 550 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 551 | |
| 552 | static void configure_thermal_target(void) |
| 553 | { |
| 554 | struct cpu_intel_haswell_config *conf; |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 555 | struct device *lapic; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 556 | msr_t msr; |
| 557 | |
| 558 | /* Find pointer to CPU configuration */ |
| 559 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 560 | if (!lapic || !lapic->chip_info) |
| 561 | return; |
| 562 | conf = lapic->chip_info; |
| 563 | |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 564 | /* Set TCC activation offset if supported */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 565 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 566 | if ((msr.lo & (1 << 30)) && conf->tcc_offset) { |
| 567 | msr = rdmsr(MSR_TEMPERATURE_TARGET); |
| 568 | msr.lo &= ~(0xf << 24); /* Bits 27:24 */ |
| 569 | msr.lo |= (conf->tcc_offset & 0xf) << 24; |
| 570 | wrmsr(MSR_TEMPERATURE_TARGET, msr); |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | static void configure_misc(void) |
| 575 | { |
| 576 | msr_t msr; |
| 577 | |
| 578 | msr = rdmsr(IA32_MISC_ENABLE); |
| 579 | msr.lo |= (1 << 0); /* Fast String enable */ |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 580 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 581 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 582 | wrmsr(IA32_MISC_ENABLE, msr); |
| 583 | |
| 584 | /* Disable Thermal interrupts */ |
| 585 | msr.lo = 0; |
| 586 | msr.hi = 0; |
| 587 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 588 | |
| 589 | /* Enable package critical interrupt only */ |
| 590 | msr.lo = 1 << 4; |
| 591 | msr.hi = 0; |
| 592 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 593 | } |
| 594 | |
| 595 | static void enable_lapic_tpr(void) |
| 596 | { |
| 597 | msr_t msr; |
| 598 | |
| 599 | msr = rdmsr(MSR_PIC_MSG_CONTROL); |
| 600 | msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ |
| 601 | wrmsr(MSR_PIC_MSG_CONTROL, msr); |
| 602 | } |
| 603 | |
| 604 | static void configure_dca_cap(void) |
| 605 | { |
| 606 | struct cpuid_result cpuid_regs; |
| 607 | msr_t msr; |
| 608 | |
| 609 | /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ |
| 610 | cpuid_regs = cpuid(1); |
| 611 | if (cpuid_regs.ecx & (1 << 18)) { |
| 612 | msr = rdmsr(IA32_PLATFORM_DCA_CAP); |
| 613 | msr.lo |= 1; |
| 614 | wrmsr(IA32_PLATFORM_DCA_CAP, msr); |
| 615 | } |
| 616 | } |
| 617 | |
| 618 | static void set_max_ratio(void) |
| 619 | { |
| 620 | msr_t msr, perf_ctl; |
| 621 | |
| 622 | perf_ctl.hi = 0; |
| 623 | |
| 624 | /* Check for configurable TDP option */ |
| 625 | if (cpu_config_tdp_levels()) { |
| 626 | /* Set to nominal TDP ratio */ |
| 627 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 628 | perf_ctl.lo = (msr.lo & 0xff) << 8; |
| 629 | } else { |
| 630 | /* Platform Info bits 15:8 give max ratio */ |
| 631 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 632 | perf_ctl.lo = msr.lo & 0xff00; |
| 633 | } |
| 634 | wrmsr(IA32_PERF_CTL, perf_ctl); |
| 635 | |
| 636 | printk(BIOS_DEBUG, "haswell: frequency set to %d\n", |
| 637 | ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); |
| 638 | } |
| 639 | |
| 640 | static void set_energy_perf_bias(u8 policy) |
| 641 | { |
| 642 | msr_t msr; |
Aaron Durbin | dc278f8 | 2012-12-11 17:15:13 -0600 | [diff] [blame] | 643 | int ecx; |
| 644 | |
| 645 | /* Determine if energy efficient policy is supported. */ |
| 646 | ecx = cpuid_ecx(0x6); |
| 647 | if (!(ecx & (1 << 3))) |
| 648 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 649 | |
| 650 | /* Energy Policy is bits 3:0 */ |
| 651 | msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); |
| 652 | msr.lo &= ~0xf; |
| 653 | msr.lo |= policy & 0xf; |
| 654 | wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); |
| 655 | |
| 656 | printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", |
| 657 | policy); |
| 658 | } |
| 659 | |
| 660 | static void configure_mca(void) |
| 661 | { |
| 662 | msr_t msr; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 663 | const unsigned int mcg_cap_msr = 0x179; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 664 | int i; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 665 | int num_banks; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 666 | |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 667 | msr = rdmsr(mcg_cap_msr); |
| 668 | num_banks = msr.lo & 0xff; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 669 | msr.lo = msr.hi = 0; |
Aaron Durbin | 24614af | 2013-01-12 01:07:28 -0600 | [diff] [blame] | 670 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 671 | * of these banks are core vs package scope. For now every CPU clears |
| 672 | * every bank. */ |
| 673 | for (i = 0; i < num_banks; i++) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 674 | wrmsr(IA32_MC0_STATUS + (i * 4), msr); |
| 675 | } |
| 676 | |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 677 | /* All CPUs including BSP will run the following function. */ |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 678 | static void haswell_init(struct device *cpu) |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 679 | { |
| 680 | /* Clear out pending MCEs */ |
| 681 | configure_mca(); |
| 682 | |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 683 | /* Enable the local CPU APICs */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 684 | enable_lapic_tpr(); |
| 685 | setup_lapic(); |
| 686 | |
Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 687 | /* Set virtualization based on Kconfig option */ |
| 688 | set_vmx(); |
Matt DeVillier | b2a14fb | 2014-07-07 18:48:16 -0500 | [diff] [blame] | 689 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 690 | /* Configure C States */ |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 691 | configure_c_states(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 692 | |
| 693 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 694 | configure_misc(); |
| 695 | |
| 696 | /* Thermal throttle activation offset */ |
| 697 | configure_thermal_target(); |
| 698 | |
| 699 | /* Enable Direct Cache Access */ |
| 700 | configure_dca_cap(); |
| 701 | |
| 702 | /* Set energy policy */ |
| 703 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 704 | |
| 705 | /* Set Max Ratio */ |
| 706 | set_max_ratio(); |
| 707 | |
| 708 | /* Enable Turbo */ |
| 709 | enable_turbo(); |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 710 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 711 | |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 712 | /* MP initialization support. */ |
| 713 | static const void *microcode_patch; |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 714 | static int ht_disabled; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 715 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 716 | static void pre_mp_init(void) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 717 | { |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 718 | /* Setup MTRRs based on physical address size. */ |
| 719 | x86_setup_mtrrs_with_detect(); |
| 720 | x86_mtrr_check(); |
| 721 | |
| 722 | initialize_vr_config(); |
| 723 | |
| 724 | if (haswell_is_ult()) { |
| 725 | calibrate_24mhz_bclk(); |
| 726 | configure_pch_power_sharing(); |
| 727 | } |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 728 | } |
| 729 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 730 | static int get_cpu_count(void) |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 731 | { |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 732 | msr_t msr; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 733 | int num_threads; |
| 734 | int num_cores; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 735 | |
| 736 | msr = rdmsr(CORE_THREAD_COUNT_MSR); |
| 737 | num_threads = (msr.lo >> 0) & 0xffff; |
| 738 | num_cores = (msr.lo >> 16) & 0xffff; |
| 739 | printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", |
| 740 | num_cores, num_threads); |
| 741 | |
| 742 | ht_disabled = num_threads == num_cores; |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 743 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 744 | return num_threads; |
| 745 | } |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 746 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 747 | static void get_microcode_info(const void **microcode, int *parallel) |
| 748 | { |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 749 | microcode_patch = intel_microcode_find(); |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 750 | *microcode = microcode_patch; |
| 751 | *parallel = 1; |
| 752 | } |
Aaron Durbin | 7af2069 | 2013-01-14 14:54:41 -0600 | [diff] [blame] | 753 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 754 | static int adjust_apic_id(int index, int apic_id) |
| 755 | { |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 756 | if (ht_disabled) |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 757 | return 2 * index; |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 758 | else |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 759 | return index; |
| 760 | } |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 761 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 762 | static void per_cpu_smm_trigger(void) |
| 763 | { |
| 764 | /* Relocate the SMM handler. */ |
| 765 | smm_relocate(); |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 766 | |
Aaron Durbin | 463af33 | 2016-05-03 17:26:35 -0500 | [diff] [blame] | 767 | /* After SMM relocation a 2nd microcode load is required. */ |
| 768 | intel_microcode_load_unlocked(microcode_patch); |
| 769 | } |
| 770 | |
| 771 | static void post_mp_init(void) |
| 772 | { |
| 773 | /* Now that all APs have been relocated as well as the BSP let SMIs |
| 774 | * start flowing. */ |
| 775 | southbridge_smm_enable_smi(); |
| 776 | |
| 777 | /* Lock down the SMRAM space. */ |
| 778 | smm_lock(); |
| 779 | } |
| 780 | |
| 781 | static const struct mp_ops mp_ops = { |
| 782 | .pre_mp_init = pre_mp_init, |
| 783 | .get_cpu_count = get_cpu_count, |
| 784 | .get_smm_info = smm_info, |
| 785 | .get_microcode_info = get_microcode_info, |
| 786 | .adjust_cpu_apic_entry = adjust_apic_id, |
| 787 | .pre_mp_smm_init = smm_initialize, |
| 788 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 789 | .relocation_handler = smm_relocation_handler, |
| 790 | .post_mp_init = post_mp_init, |
| 791 | }; |
| 792 | |
| 793 | void bsp_init_and_start_aps(struct bus *cpu_bus) |
| 794 | { |
| 795 | if (mp_init_with_smm(cpu_bus, &mp_ops)) { |
Aaron Durbin | 014baea | 2014-03-28 22:01:05 -0500 | [diff] [blame] | 796 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Aaron Durbin | 305b1f0 | 2013-01-15 08:27:05 -0600 | [diff] [blame] | 797 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 798 | } |
| 799 | |
| 800 | static struct device_operations cpu_dev_ops = { |
| 801 | .init = haswell_init, |
| 802 | }; |
| 803 | |
| 804 | static struct cpu_device_id cpu_table[] = { |
| 805 | { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ |
| 806 | { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ |
Duncan Laurie | 51254049 | 2012-12-17 11:24:45 -0800 | [diff] [blame] | 807 | { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ |
| 808 | { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 809 | { 0, 0 }, |
| 810 | }; |
| 811 | |
| 812 | static const struct cpu_driver driver __cpu_driver = { |
| 813 | .ops = &cpu_dev_ops, |
| 814 | .id_table = cpu_table, |
Aaron Durbin | 7c35131 | 2013-04-10 14:46:25 -0500 | [diff] [blame] | 815 | .cstates = cstate_map, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 816 | }; |