Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 17 | #include <chip.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 21 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | #include <soc/pci_devs.h> |
| 23 | #include <soc/ramstage.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 24 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 25 | static void pci_domain_set_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 26 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 27 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 28 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 29 | assign_resources(dev->link_list); |
| 30 | } |
| 31 | |
| 32 | static struct device_operations pci_domain_ops = { |
| 33 | .read_resources = pci_domain_read_resources, |
| 34 | .set_resources = pci_domain_set_resources, |
| 35 | .enable_resources = NULL, |
| 36 | .init = NULL, |
| 37 | .scan_bus = pci_domain_scan_bus, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 38 | }; |
| 39 | |
| 40 | static struct device_operations cpu_bus_ops = { |
Elyes HAOUAS | b6fa7a2 | 2018-12-07 12:21:18 +0100 | [diff] [blame] | 41 | .read_resources = DEVICE_NOOP, |
| 42 | .set_resources = DEVICE_NOOP, |
| 43 | .enable_resources = DEVICE_NOOP, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 44 | .init = soc_init_cpus |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 45 | }; |
| 46 | |
| 47 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 48 | static void enable_dev(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 49 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 50 | printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 51 | __FILE__, __func__, |
| 52 | dev_name(dev), dev->path.type); |
| 53 | printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", |
| 54 | pci_read_config16(dev, PCI_VENDOR_ID), |
| 55 | pci_read_config16(dev, PCI_DEVICE_ID)); |
| 56 | printk(BIOS_SPEW, "class: 0x%02x %s\n" |
| 57 | "subclass: 0x%02x %s\n" |
| 58 | "prog: 0x%02x\n" |
| 59 | "revision: 0x%02x\n", |
| 60 | pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, |
| 61 | get_pci_class_name(dev), |
| 62 | pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, |
| 63 | get_pci_subclass_name(dev), |
| 64 | pci_read_config8(dev, PCI_CLASS_PROG), |
| 65 | pci_read_config8(dev, PCI_REVISION_ID)); |
| 66 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 67 | /* Set the operations if it is a special bus type */ |
| 68 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 69 | dev->ops = &pci_domain_ops; |
| 70 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 71 | dev->ops = &cpu_bus_ops; |
| 72 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 73 | /* Handle south cluster enablement. */ |
| 74 | if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && |
| 75 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 76 | southcluster_enable_dev(dev); |
| 77 | } |
| 78 | } |
| 79 | } |
| 80 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 81 | __weak void board_silicon_USB2_override(SILICON_INIT_UPD *params) |
Matt DeVillier | 2c8ac22 | 2017-08-26 04:53:35 -0500 | [diff] [blame] | 82 | { |
| 83 | } |
| 84 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 85 | void soc_silicon_init_params(SILICON_INIT_UPD *params) |
| 86 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 87 | struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Ravi Sarawadi | d077b58 | 2015-09-09 14:12:16 -0700 | [diff] [blame] | 88 | struct soc_intel_braswell_config *config; |
| 89 | |
| 90 | if (!dev) { |
| 91 | printk(BIOS_ERR, |
| 92 | "Error! Device (%s) not found, " |
| 93 | "soc_silicon_init_params!\n", dev_path(dev)); |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | config = dev->chip_info; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 98 | |
| 99 | /* Set the parameters for SiliconInit */ |
| 100 | printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); |
| 101 | params->PcdSdcardMode = config->PcdSdcardMode; |
| 102 | params->PcdEnableHsuart0 = config->PcdEnableHsuart0; |
| 103 | params->PcdEnableHsuart1 = config->PcdEnableHsuart1; |
| 104 | params->PcdEnableAzalia = config->PcdEnableAzalia; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 105 | params->PcdEnableSata = config->PcdEnableSata; |
| 106 | params->PcdEnableXhci = config->PcdEnableXhci; |
| 107 | params->PcdEnableLpe = config->PcdEnableLpe; |
| 108 | params->PcdEnableDma0 = config->PcdEnableDma0; |
| 109 | params->PcdEnableDma1 = config->PcdEnableDma1; |
| 110 | params->PcdEnableI2C0 = config->PcdEnableI2C0; |
| 111 | params->PcdEnableI2C1 = config->PcdEnableI2C1; |
| 112 | params->PcdEnableI2C2 = config->PcdEnableI2C2; |
| 113 | params->PcdEnableI2C3 = config->PcdEnableI2C3; |
| 114 | params->PcdEnableI2C4 = config->PcdEnableI2C4; |
| 115 | params->PcdEnableI2C5 = config->PcdEnableI2C5; |
| 116 | params->PcdEnableI2C6 = config->PcdEnableI2C6; |
Subrata Banik | 13cd331 | 2015-08-07 18:22:54 +0530 | [diff] [blame] | 117 | params->GraphicsConfigPtr = 0; |
| 118 | params->AzaliaConfigPtr = 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 119 | params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; |
| 120 | params->ChvSvidConfig = config->ChvSvidConfig; |
| 121 | params->DptfDisable = config->DptfDisable; |
| 122 | params->PcdEmmcMode = config->PcdEmmcMode; |
| 123 | params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; |
| 124 | params->PcdDispClkSsc = config->PcdDispClkSsc; |
| 125 | params->PcdSataClkSsc = config->PcdSataClkSsc; |
| 126 | params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; |
| 127 | params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; |
| 128 | params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; |
| 129 | params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 130 | if (config->D0Usb2Port0PerPortRXISet != 0) |
| 131 | params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet; |
| 132 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 133 | params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; |
| 134 | params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; |
| 135 | params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; |
| 136 | params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 137 | if (config->D0Usb2Port1PerPortRXISet != 0) |
| 138 | params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet; |
| 139 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 140 | params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; |
| 141 | params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; |
| 142 | params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; |
| 143 | params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 144 | if (config->D0Usb2Port2PerPortRXISet != 0) |
| 145 | params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet; |
| 146 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 147 | params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; |
| 148 | params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; |
| 149 | params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; |
| 150 | params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 151 | if (config->D0Usb2Port3PerPortRXISet != 0) |
| 152 | params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet; |
| 153 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 154 | params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; |
| 155 | params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; |
| 156 | params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; |
| 157 | params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 158 | if (config->D0Usb2Port4PerPortRXISet != 0) |
| 159 | params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet; |
| 160 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 161 | params->Usb3Lane0Ow2tapgen2deemph3p5 = |
| 162 | config->Usb3Lane0Ow2tapgen2deemph3p5; |
| 163 | params->Usb3Lane1Ow2tapgen2deemph3p5 = |
| 164 | config->Usb3Lane1Ow2tapgen2deemph3p5; |
| 165 | params->Usb3Lane2Ow2tapgen2deemph3p5 = |
| 166 | config->Usb3Lane2Ow2tapgen2deemph3p5; |
| 167 | params->Usb3Lane3Ow2tapgen2deemph3p5 = |
| 168 | config->Usb3Lane3Ow2tapgen2deemph3p5; |
| 169 | params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; |
| 170 | params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; |
| 171 | params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; |
| 172 | params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; |
| 173 | params->PcdPchSsicEnable = config->PcdPchSsicEnable; |
| 174 | params->PcdLogoPtr = config->PcdLogoPtr; |
| 175 | params->PcdLogoSize = config->PcdLogoSize; |
| 176 | params->PcdRtcLock = config->PcdRtcLock; |
| 177 | params->PMIC_I2CBus = config->PMIC_I2CBus; |
| 178 | params->ISPEnable = config->ISPEnable; |
| 179 | params->ISPPciDevConfig = config->ISPPciDevConfig; |
Divya Sasidharan | 89a6685 | 2015-10-28 15:02:35 -0700 | [diff] [blame] | 180 | params->PcdSdDetectChk = config->PcdSdDetectChk; |
Divagar Mohandass | 0c68530 | 2016-02-08 16:09:21 +0530 | [diff] [blame] | 181 | params->I2C0Frequency = config->I2C0Frequency; |
| 182 | params->I2C1Frequency = config->I2C1Frequency; |
| 183 | params->I2C2Frequency = config->I2C2Frequency; |
| 184 | params->I2C3Frequency = config->I2C3Frequency; |
| 185 | params->I2C4Frequency = config->I2C4Frequency; |
| 186 | params->I2C5Frequency = config->I2C5Frequency; |
| 187 | params->I2C6Frequency = config->I2C6Frequency; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 188 | |
Matt DeVillier | 2c8ac22 | 2017-08-26 04:53:35 -0500 | [diff] [blame] | 189 | board_silicon_USB2_override(params); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, |
| 193 | SILICON_INIT_UPD *new) |
| 194 | { |
| 195 | /* Display the parameters for SiliconInit */ |
| 196 | printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 197 | fsp_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 198 | new->PcdSdcardMode); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 199 | fsp_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 200 | new->PcdEnableHsuart0); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 201 | fsp_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 202 | new->PcdEnableHsuart1); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 203 | fsp_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 204 | new->PcdEnableAzalia); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 205 | fsp_display_upd_value("AzaliaConfigPtr", 4, |
Subrata Banik | 13cd331 | 2015-08-07 18:22:54 +0530 | [diff] [blame] | 206 | (uint32_t)old->AzaliaConfigPtr, |
| 207 | (uint32_t)new->AzaliaConfigPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 208 | fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 209 | new->PcdEnableSata); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 210 | fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 211 | new->PcdEnableXhci); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 212 | fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 213 | new->PcdEnableLpe); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 214 | fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 215 | new->PcdEnableDma0); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 216 | fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 217 | new->PcdEnableDma1); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 218 | fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 219 | new->PcdEnableI2C0); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 220 | fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 221 | new->PcdEnableI2C1); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 222 | fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 223 | new->PcdEnableI2C2); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 224 | fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 225 | new->PcdEnableI2C3); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 226 | fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 227 | new->PcdEnableI2C4); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 228 | fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 229 | new->PcdEnableI2C5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 230 | fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 231 | new->PcdEnableI2C6); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 232 | fsp_display_upd_value("PcdGraphicsConfigPtr", 4, |
Subrata Banik | 13cd331 | 2015-08-07 18:22:54 +0530 | [diff] [blame] | 233 | old->GraphicsConfigPtr, new->GraphicsConfigPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 234 | fsp_display_upd_value("GpioFamilyInitTablePtr", 4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 235 | (uint32_t)old->GpioFamilyInitTablePtr, |
| 236 | (uint32_t)new->GpioFamilyInitTablePtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 237 | fsp_display_upd_value("GpioPadInitTablePtr", 4, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 238 | (uint32_t)old->GpioPadInitTablePtr, |
| 239 | (uint32_t)new->GpioPadInitTablePtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 240 | fsp_display_upd_value("PunitPwrConfigDisable", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 241 | old->PunitPwrConfigDisable, |
| 242 | new->PunitPwrConfigDisable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 243 | fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 244 | new->ChvSvidConfig); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 245 | fsp_display_upd_value("DptfDisable", 1, old->DptfDisable, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 246 | new->DptfDisable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 247 | fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 248 | new->PcdEmmcMode); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 249 | fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 250 | new->PcdUsb3ClkSsc); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 251 | fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 252 | new->PcdDispClkSsc); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 253 | fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 254 | new->PcdSataClkSsc); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 255 | fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 256 | old->Usb2Port0PerPortPeTxiSet, |
| 257 | new->Usb2Port0PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 258 | fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 259 | old->Usb2Port0PerPortTxiSet, |
| 260 | new->Usb2Port0PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 261 | fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 262 | old->Usb2Port0IUsbTxEmphasisEn, |
| 263 | new->Usb2Port0IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 264 | fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 265 | old->Usb2Port0PerPortTxPeHalf, |
| 266 | new->Usb2Port0PerPortTxPeHalf); |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 267 | fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1, |
| 268 | old->D0Usb2Port0PerPortRXISet, |
| 269 | new->D0Usb2Port0PerPortRXISet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 270 | fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 271 | old->Usb2Port1PerPortPeTxiSet, |
| 272 | new->Usb2Port1PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 273 | fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 274 | old->Usb2Port1PerPortTxiSet, |
| 275 | new->Usb2Port1PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 276 | fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 277 | old->Usb2Port1IUsbTxEmphasisEn, |
| 278 | new->Usb2Port1IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 279 | fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 280 | old->Usb2Port1PerPortTxPeHalf, |
| 281 | new->Usb2Port1PerPortTxPeHalf); |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 282 | fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1, |
| 283 | old->D0Usb2Port1PerPortRXISet, |
| 284 | new->D0Usb2Port1PerPortRXISet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 285 | fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 286 | old->Usb2Port2PerPortPeTxiSet, |
| 287 | new->Usb2Port2PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 288 | fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 289 | old->Usb2Port2PerPortTxiSet, |
| 290 | new->Usb2Port2PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 291 | fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 292 | old->Usb2Port2IUsbTxEmphasisEn, |
| 293 | new->Usb2Port2IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 294 | fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 295 | old->Usb2Port2PerPortTxPeHalf, |
| 296 | new->Usb2Port2PerPortTxPeHalf); |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 297 | fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1, |
| 298 | old->D0Usb2Port2PerPortRXISet, |
| 299 | new->D0Usb2Port2PerPortRXISet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 300 | fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 301 | old->Usb2Port3PerPortPeTxiSet, |
| 302 | new->Usb2Port3PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 303 | fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 304 | old->Usb2Port3PerPortTxiSet, |
| 305 | new->Usb2Port3PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 306 | fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 307 | old->Usb2Port3IUsbTxEmphasisEn, |
| 308 | new->Usb2Port3IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 309 | fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 310 | old->Usb2Port3PerPortTxPeHalf, |
| 311 | new->Usb2Port3PerPortTxPeHalf); |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 312 | fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1, |
| 313 | old->D0Usb2Port3PerPortRXISet, |
| 314 | new->D0Usb2Port3PerPortRXISet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 315 | fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 316 | old->Usb2Port4PerPortPeTxiSet, |
| 317 | new->Usb2Port4PerPortPeTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 318 | fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 319 | old->Usb2Port4PerPortTxiSet, |
| 320 | new->Usb2Port4PerPortTxiSet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 321 | fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 322 | old->Usb2Port4IUsbTxEmphasisEn, |
| 323 | new->Usb2Port4IUsbTxEmphasisEn); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 324 | fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 325 | old->Usb2Port4PerPortTxPeHalf, |
| 326 | new->Usb2Port4PerPortTxPeHalf); |
Kevin Chiu | 348a6d5 | 2016-06-30 14:50:52 +0800 | [diff] [blame] | 327 | fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1, |
| 328 | old->D0Usb2Port4PerPortRXISet, |
| 329 | new->D0Usb2Port4PerPortRXISet); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 330 | fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 331 | old->Usb3Lane0Ow2tapgen2deemph3p5, |
| 332 | new->Usb3Lane0Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 333 | fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 334 | old->Usb3Lane1Ow2tapgen2deemph3p5, |
| 335 | new->Usb3Lane1Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 336 | fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 337 | old->Usb3Lane2Ow2tapgen2deemph3p5, |
| 338 | new->Usb3Lane2Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 339 | fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 340 | old->Usb3Lane3Ow2tapgen2deemph3p5, |
| 341 | new->Usb3Lane3Ow2tapgen2deemph3p5); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 342 | fsp_display_upd_value("PcdSataInterfaceSpeed", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 343 | old->PcdSataInterfaceSpeed, |
| 344 | new->PcdSataInterfaceSpeed); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 345 | fsp_display_upd_value("PcdPchUsbSsicPort", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 346 | old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 347 | fsp_display_upd_value("PcdPchUsbHsicPort", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 348 | old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 349 | fsp_display_upd_value("PcdPcieRootPortSpeed", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 350 | old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 351 | fsp_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 352 | new->PcdPchSsicEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 353 | fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 354 | new->PcdLogoPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 355 | fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 356 | new->PcdLogoSize); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 357 | fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 358 | new->PcdRtcLock); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 359 | fsp_display_upd_value("PMIC_I2CBus", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 360 | old->PMIC_I2CBus, new->PMIC_I2CBus); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 361 | fsp_display_upd_value("ISPEnable", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 362 | old->ISPEnable, new->ISPEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 363 | fsp_display_upd_value("ISPPciDevConfig", 1, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 364 | old->ISPPciDevConfig, new->ISPPciDevConfig); |
Divya Sasidharan | 89a6685 | 2015-10-28 15:02:35 -0700 | [diff] [blame] | 365 | fsp_display_upd_value("PcdSdDetectChk", 1, |
| 366 | old->PcdSdDetectChk, new->PcdSdDetectChk); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 367 | } |
| 368 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 369 | /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ |
| 370 | static void soc_init(void *chip_info) |
| 371 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 372 | printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); |
| 373 | soc_init_pre_device(chip_info); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 374 | } |
| 375 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 376 | struct chip_operations soc_intel_braswell_ops = { |
| 377 | CHIP_NAME("Intel Braswell SoC") |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 378 | .enable_dev = enable_dev, |
| 379 | .init = soc_init, |
| 380 | }; |
| 381 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 382 | static void pci_set_subsystem(struct device *dev, unsigned int vendor, |
Lee Leahy | 1072e7d | 2017-03-16 17:35:32 -0700 | [diff] [blame] | 383 | unsigned int device) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 384 | { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 385 | printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 386 | __FILE__, __func__, dev_name(dev), vendor, device); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 387 | if (!vendor || !device) { |
| 388 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 389 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 390 | } else { |
| 391 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 392 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 393 | } |
| 394 | } |
| 395 | |
| 396 | struct pci_operations soc_pci_ops = { |
| 397 | .set_subsystem = &pci_set_subsystem, |
| 398 | }; |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 399 | |
| 400 | /** |
| 401 | Return SoC stepping type |
| 402 | |
| 403 | @retval SOC_STEPPING SoC stepping type |
| 404 | **/ |
| 405 | int SocStepping(void) |
| 406 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 407 | struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); |
Matt DeVillier | 143a836 | 2017-08-26 04:47:15 -0500 | [diff] [blame] | 408 | u8 revid = pci_read_config8(dev, 0x8); |
| 409 | |
| 410 | switch (revid & B_PCH_LPC_RID_STEPPING_MASK) { |
| 411 | case V_PCH_LPC_RID_A0: |
| 412 | return SocA0; |
| 413 | case V_PCH_LPC_RID_A1: |
| 414 | return SocA1; |
| 415 | case V_PCH_LPC_RID_A2: |
| 416 | return SocA2; |
| 417 | case V_PCH_LPC_RID_A3: |
| 418 | return SocA3; |
| 419 | case V_PCH_LPC_RID_A4: |
| 420 | return SocA4; |
| 421 | case V_PCH_LPC_RID_A5: |
| 422 | return SocA5; |
| 423 | case V_PCH_LPC_RID_A6: |
| 424 | return SocA6; |
| 425 | case V_PCH_LPC_RID_A7: |
| 426 | return SocA7; |
| 427 | case V_PCH_LPC_RID_B0: |
| 428 | return SocB0; |
| 429 | case V_PCH_LPC_RID_B1: |
| 430 | return SocB1; |
| 431 | case V_PCH_LPC_RID_B2: |
| 432 | return SocB2; |
| 433 | case V_PCH_LPC_RID_B3: |
| 434 | return SocB3; |
| 435 | case V_PCH_LPC_RID_B4: |
| 436 | return SocB4; |
| 437 | case V_PCH_LPC_RID_B5: |
| 438 | return SocB5; |
| 439 | case V_PCH_LPC_RID_B6: |
| 440 | return SocB6; |
| 441 | case V_PCH_LPC_RID_B7: |
| 442 | return SocB7; |
| 443 | case V_PCH_LPC_RID_C0: |
| 444 | return SocC0; |
| 445 | case V_PCH_LPC_RID_C1: |
| 446 | return SocC1; |
| 447 | case V_PCH_LPC_RID_C2: |
| 448 | return SocC2; |
| 449 | case V_PCH_LPC_RID_C3: |
| 450 | return SocC3; |
| 451 | case V_PCH_LPC_RID_C4: |
| 452 | return SocC4; |
| 453 | case V_PCH_LPC_RID_C5: |
| 454 | return SocC5; |
| 455 | case V_PCH_LPC_RID_C6: |
| 456 | return SocC6; |
| 457 | case V_PCH_LPC_RID_C7: |
| 458 | return SocC7; |
| 459 | case V_PCH_LPC_RID_D0: |
| 460 | return SocD0; |
| 461 | case V_PCH_LPC_RID_D1: |
| 462 | return SocD1; |
| 463 | case V_PCH_LPC_RID_D2: |
| 464 | return SocD2; |
| 465 | case V_PCH_LPC_RID_D3: |
| 466 | return SocD3; |
| 467 | case V_PCH_LPC_RID_D4: |
| 468 | return SocD4; |
| 469 | case V_PCH_LPC_RID_D5: |
| 470 | return SocD5; |
| 471 | case V_PCH_LPC_RID_D6: |
| 472 | return SocD6; |
| 473 | case V_PCH_LPC_RID_D7: |
| 474 | return SocD7; |
| 475 | default: |
| 476 | return SocSteppingMax; |
| 477 | } |
| 478 | } |