soc/intel/braswell: Add I2C clock config options
Cherry-pick from Chromium commit e3c1ec2.
This change includes
- FSP config parameters to configure I2C clock speed.
- Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz.
Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390
Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 4d7b906..91cb384 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -162,6 +162,13 @@
params->ISPEnable = config->ISPEnable;
params->ISPPciDevConfig = config->ISPPciDevConfig;
params->PcdSdDetectChk = config->PcdSdDetectChk;
+ params->I2C0Frequency = config->I2C0Frequency;
+ params->I2C1Frequency = config->I2C1Frequency;
+ params->I2C2Frequency = config->I2C2Frequency;
+ params->I2C3Frequency = config->I2C3Frequency;
+ params->I2C4Frequency = config->I2C4Frequency;
+ params->I2C5Frequency = config->I2C5Frequency;
+ params->I2C6Frequency = config->I2C6Frequency;
}
void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,