commit 13cd3310a55c5683fb0b1176444ad8f5e5243945
author Subrata Banik <subrata.banik@intel.com> Fri Aug 07 18:22:54 2015 +0530
committer Aaron Durbin <adurbin@gmail.com> Sun Oct 11 23:55:27 2015 +0000
tree f2a2f4e423bd0e880d5d43efd3cf077d605ffb91
parent 951f2d3ebb391bf4b08cb0073c96689fa453a94d

Braswell: Modify CB to accomodate new FSPv83

Latest FSPv83 made some change related to UPD/VPD
need this patch to align those

BUG=None
TEST=Build and Boot Cyan System
BRANCH=strago-7287.B
CQ-DEPEND=CL:*226897

Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291394
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303137
Original-Commit-Ready: John Zhao <john.zhao@intel.com>
Original-Tested-by: John Zhao <john.zhao@intel.com>

Change-Id: I9920eea84b802699454850bfde489668201ffeb6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11813
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/intel/braswell/chip.c

diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 6f22740..822ee78 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -96,7 +96,6 @@
 	params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
 	params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
 	params->PcdEnableAzalia = config->PcdEnableAzalia;
-	params->AzaliaConfigPtr = config->AzaliaConfigPtr;
 	params->PcdEnableSata = config->PcdEnableSata;
 	params->PcdEnableXhci = config->PcdEnableXhci;
 	params->PcdEnableLpe = config->PcdEnableLpe;
@@ -109,7 +108,8 @@
 	params->PcdEnableI2C4 = config->PcdEnableI2C4;
 	params->PcdEnableI2C5 = config->PcdEnableI2C5;
 	params->PcdEnableI2C6 = config->PcdEnableI2C6;
-	params->PcdGraphicsConfigPtr = config->PcdGraphicsConfigPtr;
+	params->GraphicsConfigPtr = 0;
+	params->AzaliaConfigPtr = 0;
 	params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
 	params->ChvSvidConfig = config->ChvSvidConfig;
 	params->DptfDisable = config->DptfDisable;
@@ -171,11 +171,9 @@
 		new->PcdEnableHsuart1);
 	soc_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia,
 		new->PcdEnableAzalia);
-	soc_display_upd_value("AzaliaVerbTablePtr", 4,
-		(uint32_t)old->AzaliaVerbTablePtr,
-		(uint32_t)new->AzaliaVerbTablePtr);
-	soc_display_upd_value("AzaliaConfigPtr", 4, old->AzaliaConfigPtr,
-		new->AzaliaConfigPtr);
+	soc_display_upd_value("AzaliaConfigPtr", 4,
+			(uint32_t)old->AzaliaConfigPtr,
+			(uint32_t)new->AzaliaConfigPtr);
 	soc_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata,
 		new->PcdEnableSata);
 	soc_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci,
@@ -201,7 +199,7 @@
 	soc_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6,
 		new->PcdEnableI2C6);
 	soc_display_upd_value("PcdGraphicsConfigPtr", 4,
-		old->PcdGraphicsConfigPtr, new->PcdGraphicsConfigPtr);
+		old->GraphicsConfigPtr, new->GraphicsConfigPtr);
 	soc_display_upd_value("GpioFamilyInitTablePtr", 4,
 		(uint32_t)old->GpioFamilyInitTablePtr,
 		(uint32_t)new->GpioFamilyInitTablePtr);