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Lee Leahy77ff0b12015-05-05 15:07:29 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013 Google Inc.
Lee Leahy32471722015-04-20 15:20:28 -07005 * Copyright (C) 2015 Intel Corp.
Lee Leahy77ff0b12015-05-05 15:07:29 -07006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Lee Leahy77ff0b12015-05-05 15:07:29 -070015 */
16
Lee Leahy32471722015-04-20 15:20:28 -070017#include <chip.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070018#include <console/console.h>
19#include <device/device.h>
20#include <device/pci.h>
Aaron Durbin789f2b62015-09-09 17:05:06 -050021#include <fsp/util.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070022#include <soc/pci_devs.h>
23#include <soc/ramstage.h>
Lee Leahy77ff0b12015-05-05 15:07:29 -070024
Elyes HAOUASb13fac32018-05-24 22:29:44 +020025static void pci_domain_set_resources(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070026{
Elyes HAOUASa342f392018-10-17 10:56:26 +020027 printk(BIOS_SPEW, "%s/%s (%s)\n",
Lee Leahy32471722015-04-20 15:20:28 -070028 __FILE__, __func__, dev_name(dev));
Lee Leahy77ff0b12015-05-05 15:07:29 -070029 assign_resources(dev->link_list);
30}
31
32static struct device_operations pci_domain_ops = {
33 .read_resources = pci_domain_read_resources,
34 .set_resources = pci_domain_set_resources,
35 .enable_resources = NULL,
36 .init = NULL,
37 .scan_bus = pci_domain_scan_bus,
Lee Leahy77ff0b12015-05-05 15:07:29 -070038};
39
40static struct device_operations cpu_bus_ops = {
Elyes HAOUASb6fa7a22018-12-07 12:21:18 +010041 .read_resources = DEVICE_NOOP,
42 .set_resources = DEVICE_NOOP,
43 .enable_resources = DEVICE_NOOP,
Lee Leahy32471722015-04-20 15:20:28 -070044 .init = soc_init_cpus
Lee Leahy77ff0b12015-05-05 15:07:29 -070045};
46
47
Elyes HAOUASb13fac32018-05-24 22:29:44 +020048static void enable_dev(struct device *dev)
Lee Leahy77ff0b12015-05-05 15:07:29 -070049{
Elyes HAOUASa342f392018-10-17 10:56:26 +020050 printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n",
Lee Leahy32471722015-04-20 15:20:28 -070051 __FILE__, __func__,
52 dev_name(dev), dev->path.type);
53 printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",
54 pci_read_config16(dev, PCI_VENDOR_ID),
55 pci_read_config16(dev, PCI_DEVICE_ID));
56 printk(BIOS_SPEW, "class: 0x%02x %s\n"
57 "subclass: 0x%02x %s\n"
58 "prog: 0x%02x\n"
59 "revision: 0x%02x\n",
60 pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8,
61 get_pci_class_name(dev),
62 pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff,
63 get_pci_subclass_name(dev),
64 pci_read_config8(dev, PCI_CLASS_PROG),
65 pci_read_config8(dev, PCI_REVISION_ID));
66
Lee Leahy77ff0b12015-05-05 15:07:29 -070067 /* Set the operations if it is a special bus type */
68 if (dev->path.type == DEVICE_PATH_DOMAIN) {
69 dev->ops = &pci_domain_ops;
70 } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
71 dev->ops = &cpu_bus_ops;
72 } else if (dev->path.type == DEVICE_PATH_PCI) {
73 /* Handle south cluster enablement. */
74 if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
75 (dev->ops == NULL || dev->ops->enable == NULL)) {
76 southcluster_enable_dev(dev);
77 }
78 }
79}
80
Aaron Durbin64031672018-04-21 14:45:32 -060081__weak void board_silicon_USB2_override(SILICON_INIT_UPD *params)
Matt DeVillier2c8ac222017-08-26 04:53:35 -050082{
83}
84
Lee Leahy32471722015-04-20 15:20:28 -070085void soc_silicon_init_params(SILICON_INIT_UPD *params)
86{
Kyösti Mälkkic70eed12018-05-22 02:18:00 +030087 struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
Ravi Sarawadid077b582015-09-09 14:12:16 -070088 struct soc_intel_braswell_config *config;
89
90 if (!dev) {
91 printk(BIOS_ERR,
92 "Error! Device (%s) not found, "
93 "soc_silicon_init_params!\n", dev_path(dev));
94 return;
95 }
96
97 config = dev->chip_info;
Lee Leahy32471722015-04-20 15:20:28 -070098
99 /* Set the parameters for SiliconInit */
100 printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
101 params->PcdSdcardMode = config->PcdSdcardMode;
102 params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
103 params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
104 params->PcdEnableAzalia = config->PcdEnableAzalia;
Lee Leahy32471722015-04-20 15:20:28 -0700105 params->PcdEnableSata = config->PcdEnableSata;
106 params->PcdEnableXhci = config->PcdEnableXhci;
107 params->PcdEnableLpe = config->PcdEnableLpe;
108 params->PcdEnableDma0 = config->PcdEnableDma0;
109 params->PcdEnableDma1 = config->PcdEnableDma1;
110 params->PcdEnableI2C0 = config->PcdEnableI2C0;
111 params->PcdEnableI2C1 = config->PcdEnableI2C1;
112 params->PcdEnableI2C2 = config->PcdEnableI2C2;
113 params->PcdEnableI2C3 = config->PcdEnableI2C3;
114 params->PcdEnableI2C4 = config->PcdEnableI2C4;
115 params->PcdEnableI2C5 = config->PcdEnableI2C5;
116 params->PcdEnableI2C6 = config->PcdEnableI2C6;
Subrata Banik13cd3312015-08-07 18:22:54 +0530117 params->GraphicsConfigPtr = 0;
118 params->AzaliaConfigPtr = 0;
Lee Leahy32471722015-04-20 15:20:28 -0700119 params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
120 params->ChvSvidConfig = config->ChvSvidConfig;
121 params->DptfDisable = config->DptfDisable;
122 params->PcdEmmcMode = config->PcdEmmcMode;
123 params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc;
124 params->PcdDispClkSsc = config->PcdDispClkSsc;
125 params->PcdSataClkSsc = config->PcdSataClkSsc;
126 params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet;
127 params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
128 params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn;
129 params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf;
Kevin Chiu348a6d52016-06-30 14:50:52 +0800130 if (config->D0Usb2Port0PerPortRXISet != 0)
131 params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet;
132
Lee Leahy32471722015-04-20 15:20:28 -0700133 params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet;
134 params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet;
135 params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn;
136 params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf;
Kevin Chiu348a6d52016-06-30 14:50:52 +0800137 if (config->D0Usb2Port1PerPortRXISet != 0)
138 params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet;
139
Lee Leahy32471722015-04-20 15:20:28 -0700140 params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet;
141 params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet;
142 params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn;
143 params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf;
Kevin Chiu348a6d52016-06-30 14:50:52 +0800144 if (config->D0Usb2Port2PerPortRXISet != 0)
145 params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet;
146
Lee Leahy32471722015-04-20 15:20:28 -0700147 params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet;
148 params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet;
149 params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn;
150 params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf;
Kevin Chiu348a6d52016-06-30 14:50:52 +0800151 if (config->D0Usb2Port3PerPortRXISet != 0)
152 params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet;
153
Lee Leahy32471722015-04-20 15:20:28 -0700154 params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet;
155 params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet;
156 params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn;
157 params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf;
Kevin Chiu348a6d52016-06-30 14:50:52 +0800158 if (config->D0Usb2Port4PerPortRXISet != 0)
159 params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet;
160
Lee Leahy32471722015-04-20 15:20:28 -0700161 params->Usb3Lane0Ow2tapgen2deemph3p5 =
162 config->Usb3Lane0Ow2tapgen2deemph3p5;
163 params->Usb3Lane1Ow2tapgen2deemph3p5 =
164 config->Usb3Lane1Ow2tapgen2deemph3p5;
165 params->Usb3Lane2Ow2tapgen2deemph3p5 =
166 config->Usb3Lane2Ow2tapgen2deemph3p5;
167 params->Usb3Lane3Ow2tapgen2deemph3p5 =
168 config->Usb3Lane3Ow2tapgen2deemph3p5;
169 params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed;
170 params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort;
171 params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort;
172 params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed;
173 params->PcdPchSsicEnable = config->PcdPchSsicEnable;
174 params->PcdLogoPtr = config->PcdLogoPtr;
175 params->PcdLogoSize = config->PcdLogoSize;
176 params->PcdRtcLock = config->PcdRtcLock;
177 params->PMIC_I2CBus = config->PMIC_I2CBus;
178 params->ISPEnable = config->ISPEnable;
179 params->ISPPciDevConfig = config->ISPPciDevConfig;
Divya Sasidharan89a66852015-10-28 15:02:35 -0700180 params->PcdSdDetectChk = config->PcdSdDetectChk;
Divagar Mohandass0c685302016-02-08 16:09:21 +0530181 params->I2C0Frequency = config->I2C0Frequency;
182 params->I2C1Frequency = config->I2C1Frequency;
183 params->I2C2Frequency = config->I2C2Frequency;
184 params->I2C3Frequency = config->I2C3Frequency;
185 params->I2C4Frequency = config->I2C4Frequency;
186 params->I2C5Frequency = config->I2C5Frequency;
187 params->I2C6Frequency = config->I2C6Frequency;
Matt DeVillier143a8362017-08-26 04:47:15 -0500188
Matt DeVillier2c8ac222017-08-26 04:53:35 -0500189 board_silicon_USB2_override(params);
Lee Leahy32471722015-04-20 15:20:28 -0700190}
191
192void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
193 SILICON_INIT_UPD *new)
194{
195 /* Display the parameters for SiliconInit */
196 printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
Lee Leahy66208bd2015-10-15 16:17:58 -0700197 fsp_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode,
Lee Leahy32471722015-04-20 15:20:28 -0700198 new->PcdSdcardMode);
Lee Leahy66208bd2015-10-15 16:17:58 -0700199 fsp_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0,
Lee Leahy32471722015-04-20 15:20:28 -0700200 new->PcdEnableHsuart0);
Lee Leahy66208bd2015-10-15 16:17:58 -0700201 fsp_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1,
Lee Leahy32471722015-04-20 15:20:28 -0700202 new->PcdEnableHsuart1);
Lee Leahy66208bd2015-10-15 16:17:58 -0700203 fsp_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia,
Lee Leahy32471722015-04-20 15:20:28 -0700204 new->PcdEnableAzalia);
Lee Leahy66208bd2015-10-15 16:17:58 -0700205 fsp_display_upd_value("AzaliaConfigPtr", 4,
Subrata Banik13cd3312015-08-07 18:22:54 +0530206 (uint32_t)old->AzaliaConfigPtr,
207 (uint32_t)new->AzaliaConfigPtr);
Lee Leahy66208bd2015-10-15 16:17:58 -0700208 fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata,
Lee Leahy32471722015-04-20 15:20:28 -0700209 new->PcdEnableSata);
Lee Leahy66208bd2015-10-15 16:17:58 -0700210 fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci,
Lee Leahy32471722015-04-20 15:20:28 -0700211 new->PcdEnableXhci);
Lee Leahy66208bd2015-10-15 16:17:58 -0700212 fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe,
Lee Leahy32471722015-04-20 15:20:28 -0700213 new->PcdEnableLpe);
Lee Leahy66208bd2015-10-15 16:17:58 -0700214 fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0,
Lee Leahy32471722015-04-20 15:20:28 -0700215 new->PcdEnableDma0);
Lee Leahy66208bd2015-10-15 16:17:58 -0700216 fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1,
Lee Leahy32471722015-04-20 15:20:28 -0700217 new->PcdEnableDma1);
Lee Leahy66208bd2015-10-15 16:17:58 -0700218 fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0,
Lee Leahy32471722015-04-20 15:20:28 -0700219 new->PcdEnableI2C0);
Lee Leahy66208bd2015-10-15 16:17:58 -0700220 fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1,
Lee Leahy32471722015-04-20 15:20:28 -0700221 new->PcdEnableI2C1);
Lee Leahy66208bd2015-10-15 16:17:58 -0700222 fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2,
Lee Leahy32471722015-04-20 15:20:28 -0700223 new->PcdEnableI2C2);
Lee Leahy66208bd2015-10-15 16:17:58 -0700224 fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3,
Lee Leahy32471722015-04-20 15:20:28 -0700225 new->PcdEnableI2C3);
Lee Leahy66208bd2015-10-15 16:17:58 -0700226 fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4,
Lee Leahy32471722015-04-20 15:20:28 -0700227 new->PcdEnableI2C4);
Lee Leahy66208bd2015-10-15 16:17:58 -0700228 fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5,
Lee Leahy32471722015-04-20 15:20:28 -0700229 new->PcdEnableI2C5);
Lee Leahy66208bd2015-10-15 16:17:58 -0700230 fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6,
Lee Leahy32471722015-04-20 15:20:28 -0700231 new->PcdEnableI2C6);
Lee Leahy66208bd2015-10-15 16:17:58 -0700232 fsp_display_upd_value("PcdGraphicsConfigPtr", 4,
Subrata Banik13cd3312015-08-07 18:22:54 +0530233 old->GraphicsConfigPtr, new->GraphicsConfigPtr);
Lee Leahy66208bd2015-10-15 16:17:58 -0700234 fsp_display_upd_value("GpioFamilyInitTablePtr", 4,
Lee Leahy32471722015-04-20 15:20:28 -0700235 (uint32_t)old->GpioFamilyInitTablePtr,
236 (uint32_t)new->GpioFamilyInitTablePtr);
Lee Leahy66208bd2015-10-15 16:17:58 -0700237 fsp_display_upd_value("GpioPadInitTablePtr", 4,
Lee Leahy32471722015-04-20 15:20:28 -0700238 (uint32_t)old->GpioPadInitTablePtr,
239 (uint32_t)new->GpioPadInitTablePtr);
Lee Leahy66208bd2015-10-15 16:17:58 -0700240 fsp_display_upd_value("PunitPwrConfigDisable", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700241 old->PunitPwrConfigDisable,
242 new->PunitPwrConfigDisable);
Lee Leahy66208bd2015-10-15 16:17:58 -0700243 fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig,
Lee Leahy32471722015-04-20 15:20:28 -0700244 new->ChvSvidConfig);
Lee Leahy66208bd2015-10-15 16:17:58 -0700245 fsp_display_upd_value("DptfDisable", 1, old->DptfDisable,
Lee Leahy32471722015-04-20 15:20:28 -0700246 new->DptfDisable);
Lee Leahy66208bd2015-10-15 16:17:58 -0700247 fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode,
Lee Leahy32471722015-04-20 15:20:28 -0700248 new->PcdEmmcMode);
Lee Leahy66208bd2015-10-15 16:17:58 -0700249 fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc,
Lee Leahy32471722015-04-20 15:20:28 -0700250 new->PcdUsb3ClkSsc);
Lee Leahy66208bd2015-10-15 16:17:58 -0700251 fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc,
Lee Leahy32471722015-04-20 15:20:28 -0700252 new->PcdDispClkSsc);
Lee Leahy66208bd2015-10-15 16:17:58 -0700253 fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc,
Lee Leahy32471722015-04-20 15:20:28 -0700254 new->PcdSataClkSsc);
Lee Leahy66208bd2015-10-15 16:17:58 -0700255 fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700256 old->Usb2Port0PerPortPeTxiSet,
257 new->Usb2Port0PerPortPeTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700258 fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700259 old->Usb2Port0PerPortTxiSet,
260 new->Usb2Port0PerPortTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700261 fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700262 old->Usb2Port0IUsbTxEmphasisEn,
263 new->Usb2Port0IUsbTxEmphasisEn);
Lee Leahy66208bd2015-10-15 16:17:58 -0700264 fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700265 old->Usb2Port0PerPortTxPeHalf,
266 new->Usb2Port0PerPortTxPeHalf);
Kevin Chiu348a6d52016-06-30 14:50:52 +0800267 fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1,
268 old->D0Usb2Port0PerPortRXISet,
269 new->D0Usb2Port0PerPortRXISet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700270 fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700271 old->Usb2Port1PerPortPeTxiSet,
272 new->Usb2Port1PerPortPeTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700273 fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700274 old->Usb2Port1PerPortTxiSet,
275 new->Usb2Port1PerPortTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700276 fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700277 old->Usb2Port1IUsbTxEmphasisEn,
278 new->Usb2Port1IUsbTxEmphasisEn);
Lee Leahy66208bd2015-10-15 16:17:58 -0700279 fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700280 old->Usb2Port1PerPortTxPeHalf,
281 new->Usb2Port1PerPortTxPeHalf);
Kevin Chiu348a6d52016-06-30 14:50:52 +0800282 fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1,
283 old->D0Usb2Port1PerPortRXISet,
284 new->D0Usb2Port1PerPortRXISet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700285 fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700286 old->Usb2Port2PerPortPeTxiSet,
287 new->Usb2Port2PerPortPeTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700288 fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700289 old->Usb2Port2PerPortTxiSet,
290 new->Usb2Port2PerPortTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700291 fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700292 old->Usb2Port2IUsbTxEmphasisEn,
293 new->Usb2Port2IUsbTxEmphasisEn);
Lee Leahy66208bd2015-10-15 16:17:58 -0700294 fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700295 old->Usb2Port2PerPortTxPeHalf,
296 new->Usb2Port2PerPortTxPeHalf);
Kevin Chiu348a6d52016-06-30 14:50:52 +0800297 fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1,
298 old->D0Usb2Port2PerPortRXISet,
299 new->D0Usb2Port2PerPortRXISet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700300 fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700301 old->Usb2Port3PerPortPeTxiSet,
302 new->Usb2Port3PerPortPeTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700303 fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700304 old->Usb2Port3PerPortTxiSet,
305 new->Usb2Port3PerPortTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700306 fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700307 old->Usb2Port3IUsbTxEmphasisEn,
308 new->Usb2Port3IUsbTxEmphasisEn);
Lee Leahy66208bd2015-10-15 16:17:58 -0700309 fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700310 old->Usb2Port3PerPortTxPeHalf,
311 new->Usb2Port3PerPortTxPeHalf);
Kevin Chiu348a6d52016-06-30 14:50:52 +0800312 fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1,
313 old->D0Usb2Port3PerPortRXISet,
314 new->D0Usb2Port3PerPortRXISet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700315 fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700316 old->Usb2Port4PerPortPeTxiSet,
317 new->Usb2Port4PerPortPeTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700318 fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700319 old->Usb2Port4PerPortTxiSet,
320 new->Usb2Port4PerPortTxiSet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700321 fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700322 old->Usb2Port4IUsbTxEmphasisEn,
323 new->Usb2Port4IUsbTxEmphasisEn);
Lee Leahy66208bd2015-10-15 16:17:58 -0700324 fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700325 old->Usb2Port4PerPortTxPeHalf,
326 new->Usb2Port4PerPortTxPeHalf);
Kevin Chiu348a6d52016-06-30 14:50:52 +0800327 fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1,
328 old->D0Usb2Port4PerPortRXISet,
329 new->D0Usb2Port4PerPortRXISet);
Lee Leahy66208bd2015-10-15 16:17:58 -0700330 fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700331 old->Usb3Lane0Ow2tapgen2deemph3p5,
332 new->Usb3Lane0Ow2tapgen2deemph3p5);
Lee Leahy66208bd2015-10-15 16:17:58 -0700333 fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700334 old->Usb3Lane1Ow2tapgen2deemph3p5,
335 new->Usb3Lane1Ow2tapgen2deemph3p5);
Lee Leahy66208bd2015-10-15 16:17:58 -0700336 fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700337 old->Usb3Lane2Ow2tapgen2deemph3p5,
338 new->Usb3Lane2Ow2tapgen2deemph3p5);
Lee Leahy66208bd2015-10-15 16:17:58 -0700339 fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700340 old->Usb3Lane3Ow2tapgen2deemph3p5,
341 new->Usb3Lane3Ow2tapgen2deemph3p5);
Lee Leahy66208bd2015-10-15 16:17:58 -0700342 fsp_display_upd_value("PcdSataInterfaceSpeed", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700343 old->PcdSataInterfaceSpeed,
344 new->PcdSataInterfaceSpeed);
Lee Leahy66208bd2015-10-15 16:17:58 -0700345 fsp_display_upd_value("PcdPchUsbSsicPort", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700346 old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort);
Lee Leahy66208bd2015-10-15 16:17:58 -0700347 fsp_display_upd_value("PcdPchUsbHsicPort", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700348 old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort);
Lee Leahy66208bd2015-10-15 16:17:58 -0700349 fsp_display_upd_value("PcdPcieRootPortSpeed", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700350 old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed);
Lee Leahy66208bd2015-10-15 16:17:58 -0700351 fsp_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable,
Lee Leahy32471722015-04-20 15:20:28 -0700352 new->PcdPchSsicEnable);
Lee Leahy66208bd2015-10-15 16:17:58 -0700353 fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr,
Lee Leahy32471722015-04-20 15:20:28 -0700354 new->PcdLogoPtr);
Lee Leahy66208bd2015-10-15 16:17:58 -0700355 fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize,
Lee Leahy32471722015-04-20 15:20:28 -0700356 new->PcdLogoSize);
Lee Leahy66208bd2015-10-15 16:17:58 -0700357 fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock,
Lee Leahy32471722015-04-20 15:20:28 -0700358 new->PcdRtcLock);
Lee Leahy66208bd2015-10-15 16:17:58 -0700359 fsp_display_upd_value("PMIC_I2CBus", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700360 old->PMIC_I2CBus, new->PMIC_I2CBus);
Lee Leahy66208bd2015-10-15 16:17:58 -0700361 fsp_display_upd_value("ISPEnable", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700362 old->ISPEnable, new->ISPEnable);
Lee Leahy66208bd2015-10-15 16:17:58 -0700363 fsp_display_upd_value("ISPPciDevConfig", 1,
Lee Leahy32471722015-04-20 15:20:28 -0700364 old->ISPPciDevConfig, new->ISPPciDevConfig);
Divya Sasidharan89a66852015-10-28 15:02:35 -0700365 fsp_display_upd_value("PcdSdDetectChk", 1,
366 old->PcdSdDetectChk, new->PcdSdDetectChk);
Lee Leahy32471722015-04-20 15:20:28 -0700367}
368
Lee Leahy77ff0b12015-05-05 15:07:29 -0700369/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
370static void soc_init(void *chip_info)
371{
Lee Leahy32471722015-04-20 15:20:28 -0700372 printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__);
373 soc_init_pre_device(chip_info);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700374}
375
Lee Leahy32471722015-04-20 15:20:28 -0700376struct chip_operations soc_intel_braswell_ops = {
377 CHIP_NAME("Intel Braswell SoC")
Lee Leahy77ff0b12015-05-05 15:07:29 -0700378 .enable_dev = enable_dev,
379 .init = soc_init,
380};
381
Elyes HAOUASb13fac32018-05-24 22:29:44 +0200382static void pci_set_subsystem(struct device *dev, unsigned int vendor,
Lee Leahy1072e7d2017-03-16 17:35:32 -0700383 unsigned int device)
Lee Leahy77ff0b12015-05-05 15:07:29 -0700384{
Elyes HAOUASa342f392018-10-17 10:56:26 +0200385 printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n",
Lee Leahy32471722015-04-20 15:20:28 -0700386 __FILE__, __func__, dev_name(dev), vendor, device);
Lee Leahy77ff0b12015-05-05 15:07:29 -0700387 if (!vendor || !device) {
388 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
389 pci_read_config32(dev, PCI_VENDOR_ID));
390 } else {
391 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
392 ((device & 0xffff) << 16) | (vendor & 0xffff));
393 }
394}
395
396struct pci_operations soc_pci_ops = {
397 .set_subsystem = &pci_set_subsystem,
398};
Matt DeVillier143a8362017-08-26 04:47:15 -0500399
400/**
401 Return SoC stepping type
402
403 @retval SOC_STEPPING SoC stepping type
404**/
405int SocStepping(void)
406{
Kyösti Mälkkic70eed12018-05-22 02:18:00 +0300407 struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
Matt DeVillier143a8362017-08-26 04:47:15 -0500408 u8 revid = pci_read_config8(dev, 0x8);
409
410 switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {
411 case V_PCH_LPC_RID_A0:
412 return SocA0;
413 case V_PCH_LPC_RID_A1:
414 return SocA1;
415 case V_PCH_LPC_RID_A2:
416 return SocA2;
417 case V_PCH_LPC_RID_A3:
418 return SocA3;
419 case V_PCH_LPC_RID_A4:
420 return SocA4;
421 case V_PCH_LPC_RID_A5:
422 return SocA5;
423 case V_PCH_LPC_RID_A6:
424 return SocA6;
425 case V_PCH_LPC_RID_A7:
426 return SocA7;
427 case V_PCH_LPC_RID_B0:
428 return SocB0;
429 case V_PCH_LPC_RID_B1:
430 return SocB1;
431 case V_PCH_LPC_RID_B2:
432 return SocB2;
433 case V_PCH_LPC_RID_B3:
434 return SocB3;
435 case V_PCH_LPC_RID_B4:
436 return SocB4;
437 case V_PCH_LPC_RID_B5:
438 return SocB5;
439 case V_PCH_LPC_RID_B6:
440 return SocB6;
441 case V_PCH_LPC_RID_B7:
442 return SocB7;
443 case V_PCH_LPC_RID_C0:
444 return SocC0;
445 case V_PCH_LPC_RID_C1:
446 return SocC1;
447 case V_PCH_LPC_RID_C2:
448 return SocC2;
449 case V_PCH_LPC_RID_C3:
450 return SocC3;
451 case V_PCH_LPC_RID_C4:
452 return SocC4;
453 case V_PCH_LPC_RID_C5:
454 return SocC5;
455 case V_PCH_LPC_RID_C6:
456 return SocC6;
457 case V_PCH_LPC_RID_C7:
458 return SocC7;
459 case V_PCH_LPC_RID_D0:
460 return SocD0;
461 case V_PCH_LPC_RID_D1:
462 return SocD1;
463 case V_PCH_LPC_RID_D2:
464 return SocD2;
465 case V_PCH_LPC_RID_D3:
466 return SocD3;
467 case V_PCH_LPC_RID_D4:
468 return SocD4;
469 case V_PCH_LPC_RID_D5:
470 return SocD5;
471 case V_PCH_LPC_RID_D6:
472 return SocD6;
473 case V_PCH_LPC_RID_D7:
474 return SocD7;
475 default:
476 return SocSteppingMax;
477 }
478}