Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 7 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 8 | #include <acpi/acpi_gnvs.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 9 | #include <bootstate.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 10 | #include <cbmem.h> |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 11 | #include <console/console.h> |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 12 | #include <cpu/x86/smm.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 13 | #include <device/device.h> |
| 14 | #include <device/pci.h> |
| 15 | #include <device/pci_ids.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 16 | #include <pc80/mc146818rtc.h> |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 17 | #include <drivers/uart/uart8250reg.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 18 | #include <string.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 19 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 20 | #include <soc/iomap.h> |
| 21 | #include <soc/irq.h> |
| 22 | #include <soc/lpc.h> |
| 23 | #include <soc/nvs.h> |
| 24 | #include <soc/pci_devs.h> |
Angel Pons | b5320b2 | 2020-07-07 18:27:30 +0200 | [diff] [blame] | 25 | #include <soc/pm.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 26 | #include <soc/ramstage.h> |
| 27 | #include <soc/spi.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 28 | #include "chip.h" |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 29 | #include <acpi/acpigen.h> |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 30 | |
| 31 | static inline void |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 32 | add_mmio_resource(struct device *dev, int i, unsigned long addr, |
| 33 | unsigned long size) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 34 | { |
| 35 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 36 | } |
| 37 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 38 | static void sc_add_mmio_resources(struct device *dev) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 39 | { |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 40 | add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); |
| 41 | add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); |
| 42 | add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); |
| 43 | add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); |
| 44 | add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); |
| 45 | add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); |
| 46 | add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); |
| 47 | add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 48 | } |
| 49 | |
| 50 | /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ |
| 51 | #define LPC_DEFAULT_IO_RANGE_LOWER 0 |
| 52 | #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 |
| 53 | |
| 54 | static inline int io_range_in_default(int base, int size) |
| 55 | { |
| 56 | /* Does it start above the range? */ |
| 57 | if (base >= LPC_DEFAULT_IO_RANGE_UPPER) |
| 58 | return 0; |
| 59 | |
| 60 | /* Is it entirely contained? */ |
| 61 | if (base >= LPC_DEFAULT_IO_RANGE_LOWER && |
| 62 | (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) |
| 63 | return 1; |
| 64 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 65 | /* This will return not in range for partial overlaps */ |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 66 | return 0; |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * Note: this function assumes there is no overlap with the default LPC device's |
| 71 | * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. |
| 72 | */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 73 | static void sc_add_io_resource(struct device *dev, int base, int size, |
| 74 | int index) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 75 | { |
| 76 | struct resource *res; |
| 77 | |
| 78 | if (io_range_in_default(base, size)) |
| 79 | return; |
| 80 | |
| 81 | res = new_resource(dev, index); |
| 82 | res->base = base; |
| 83 | res->size = size; |
| 84 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 85 | } |
| 86 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 87 | static void sc_add_io_resources(struct device *dev) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 88 | { |
| 89 | struct resource *res; |
| 90 | |
| 91 | /* Add the default claimed IO range for the LPC device. */ |
| 92 | res = new_resource(dev, 0); |
| 93 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 94 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 95 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 96 | |
| 97 | /* GPIO */ |
Frans Hendriks | 802f43d | 2018-10-29 14:17:16 +0100 | [diff] [blame] | 98 | sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 99 | |
| 100 | /* ACPI */ |
Frans Hendriks | 802f43d | 2018-10-29 14:17:16 +0100 | [diff] [blame] | 101 | sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 102 | } |
| 103 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 104 | static void sc_read_resources(struct device *dev) |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 105 | { |
| 106 | /* Get the normal PCI resources of this device. */ |
| 107 | pci_dev_read_resources(dev); |
| 108 | |
| 109 | /* Add non-standard MMIO resources. */ |
| 110 | sc_add_mmio_resources(dev); |
| 111 | |
| 112 | /* Add IO resources. */ |
| 113 | sc_add_io_resources(dev); |
| 114 | } |
| 115 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 116 | static void sc_rtc_init(void) |
| 117 | { |
Aaron Durbin | 64b4bdd | 2017-09-15 14:24:03 -0600 | [diff] [blame] | 118 | cmos_init(rtc_failure()); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 119 | } |
| 120 | |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 121 | /* |
| 122 | * The UART hardware loses power while in suspend. Because of this the kernel |
| 123 | * can hang because it doesn't re-initialize serial ports it is using for |
| 124 | * consoles at resume time. The following function configures the UART |
| 125 | * if the hardware is enabled though it may not be the correct baud rate |
| 126 | * or configuration. This is definitely a hack, but it helps the kernel |
| 127 | * along. |
| 128 | */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 129 | static void com1_configure_resume(struct device *dev) |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 130 | { |
| 131 | const uint16_t port = 0x3f8; |
| 132 | |
Martin Roth | 99a3bba | 2014-12-07 14:57:26 -0700 | [diff] [blame] | 133 | /* Is the UART I/O port enabled? */ |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 134 | if (!(pci_read_config32(dev, UART_CONT) & 1)) |
| 135 | return; |
| 136 | |
| 137 | /* Disable interrupts */ |
| 138 | outb(0x0, port + UART8250_IER); |
| 139 | |
| 140 | /* Enable FIFOs */ |
| 141 | outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); |
| 142 | |
| 143 | /* assert DTR and RTS so the other end is happy */ |
| 144 | outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); |
| 145 | |
| 146 | /* DLAB on */ |
| 147 | outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); |
| 148 | |
| 149 | /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ |
| 150 | outb(1, port + UART8250_DLL); |
| 151 | outb(0, port + UART8250_DLM); |
| 152 | |
| 153 | /* Set to 3 for 8N1 */ |
| 154 | outb(3, port + UART8250_LCR); |
| 155 | } |
| 156 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 157 | static void sc_init(struct device *dev) |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 158 | { |
| 159 | int i; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 160 | u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); |
Alexander Couzens | 316170e | 2015-11-24 09:46:18 +0100 | [diff] [blame] | 161 | u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 162 | u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); |
| 163 | u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 164 | const struct baytrail_irq_route *ir = &global_baytrail_irq_route; |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 165 | struct soc_intel_baytrail_config *config = config_of(dev); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 166 | |
| 167 | /* Set up the PIRQ PIC routing based on static config. */ |
| 168 | for (i = 0; i < NUM_PIRQS; i++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 169 | write8(pr_base + i, ir->pic[i]); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 170 | } |
| 171 | /* Set up the per device PIRQ routing base on static config. */ |
| 172 | for (i = 0; i < NUM_IR_DEVS; i++) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 173 | write16(ir_base + i, ir->pcidev[i]); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 174 | } |
Aaron Durbin | 1af3663 | 2013-11-07 10:42:16 -0600 | [diff] [blame] | 175 | |
| 176 | /* Route SCI to IRQ9 */ |
| 177 | write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 178 | |
| 179 | sc_rtc_init(); |
| 180 | |
| 181 | if (config->disable_slp_x_stretch_sus_fail) { |
| 182 | printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); |
| 183 | write32(gen_pmcon1, |
| 184 | read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); |
| 185 | } else { |
| 186 | write32(gen_pmcon1, |
| 187 | read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); |
| 188 | } |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 189 | |
Kyösti Mälkki | 9e94dbf | 2015-01-08 20:03:18 +0200 | [diff] [blame] | 190 | if (acpi_is_wakeup_s3()) |
Kein Yuan | 3511023 | 2014-02-22 12:26:55 -0800 | [diff] [blame] | 191 | com1_configure_resume(dev); |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 192 | } |
| 193 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 194 | /* |
| 195 | * Common code for the south cluster devices. |
| 196 | */ |
| 197 | |
Martin Roth | 99a3bba | 2014-12-07 14:57:26 -0700 | [diff] [blame] | 198 | /* Set bit in function disable register to hide this device. */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 199 | static void sc_disable_devfn(struct device *dev) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 200 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 201 | u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); |
| 202 | u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 203 | uint32_t mask = 0; |
| 204 | uint32_t mask2 = 0; |
| 205 | |
| 206 | switch (dev->path.pci.devfn) { |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 207 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 208 | mask |= MMC_DIS; |
| 209 | break; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 210 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 211 | mask |= SDIO_DIS; |
| 212 | break; |
| 213 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 214 | mask |= SD_DIS; |
| 215 | break; |
| 216 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 217 | mask |= SATA_DIS; |
| 218 | break; |
| 219 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 220 | mask |= XHCI_DIS; |
| 221 | /* Disable super speed PHY when XHCI is not available. */ |
| 222 | mask2 |= USH_SS_PHY_DIS; |
| 223 | break; |
| 224 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 225 | mask |= LPE_DIS; |
| 226 | break; |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 227 | case PCI_DEVFN(MMC45_DEV, MMC45_FUNC): |
| 228 | mask |= MMC45_DIS; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 229 | break; |
| 230 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 231 | mask |= SIO_DMA1_DIS; |
| 232 | break; |
| 233 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 234 | mask |= I2C1_DIS; |
| 235 | break; |
| 236 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 237 | mask |= I2C1_DIS; |
| 238 | break; |
| 239 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 240 | mask |= I2C3_DIS; |
| 241 | break; |
| 242 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 243 | mask |= I2C4_DIS; |
| 244 | break; |
| 245 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 246 | mask |= I2C5_DIS; |
| 247 | break; |
| 248 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 249 | mask |= I2C6_DIS; |
| 250 | break; |
| 251 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 252 | mask |= I2C7_DIS; |
| 253 | break; |
| 254 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
| 255 | mask |= TXE_DIS; |
| 256 | break; |
| 257 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 258 | mask |= HDA_DIS; |
| 259 | break; |
| 260 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 261 | mask |= PCIE_PORT1_DIS; |
| 262 | break; |
| 263 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 264 | mask |= PCIE_PORT2_DIS; |
| 265 | break; |
| 266 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 267 | mask |= PCIE_PORT3_DIS; |
| 268 | break; |
| 269 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 270 | mask |= PCIE_PORT4_DIS; |
| 271 | break; |
| 272 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 273 | mask |= EHCI_DIS; |
| 274 | break; |
| 275 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 276 | mask |= SIO_DMA2_DIS; |
| 277 | break; |
| 278 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 279 | mask |= PWM1_DIS; |
| 280 | break; |
| 281 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 282 | mask |= PWM2_DIS; |
| 283 | break; |
| 284 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 285 | mask |= HSUART1_DIS; |
| 286 | break; |
| 287 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 288 | mask |= HSUART2_DIS; |
| 289 | break; |
| 290 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 291 | mask |= SPI_DIS; |
| 292 | break; |
| 293 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 294 | mask2 |= SMBUS_DIS; |
| 295 | break; |
| 296 | } |
| 297 | |
| 298 | if (mask != 0) { |
| 299 | write32(func_dis, read32(func_dis) | mask); |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 300 | /* Ensure posted write hits */ |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 301 | read32(func_dis); |
| 302 | } |
| 303 | |
| 304 | if (mask2 != 0) { |
| 305 | write32(func_dis2, read32(func_dis2) | mask2); |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 306 | /* Ensure posted write hits */ |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 307 | read32(func_dis2); |
| 308 | } |
| 309 | } |
| 310 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 311 | static inline void set_d3hot_bits(struct device *dev, int offset) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 312 | { |
| 313 | uint32_t reg8; |
| 314 | printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); |
| 315 | reg8 = pci_read_config8(dev, offset + 4); |
| 316 | reg8 |= 0x3; |
| 317 | pci_write_config8(dev, offset + 4, reg8); |
| 318 | } |
| 319 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 320 | /* |
| 321 | * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into |
| 322 | * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio. |
| 323 | */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 324 | static void hda_work_around(struct device *dev) |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 325 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 326 | u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 327 | |
| 328 | /* Need to set magic register 0x43 to 0xd7 in config space. */ |
| 329 | pci_write_config8(dev, 0x43, 0xd7); |
| 330 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 331 | /* |
| 332 | * Need to set bit 0 of GCTL to take the device out of reset. |
| 333 | * However, that requires setting up the 64-bit BAR. |
| 334 | */ |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 335 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); |
| 336 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 337 | pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 338 | write32(gctl, read32(gctl) | 0x1); |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 339 | pci_write_config16(dev, PCI_COMMAND, 0); |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 340 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); |
| 341 | } |
| 342 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 343 | static int place_device_in_d3hot(struct device *dev) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 344 | { |
Martin Roth | 57e8909 | 2019-10-23 21:45:23 -0600 | [diff] [blame] | 345 | unsigned int offset; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 346 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 347 | /* |
| 348 | * Parts of the HDA block are used for LPE audio as well. |
| 349 | * Therefore assume the HDA will never be put into D3Hot. |
| 350 | */ |
Aaron Durbin | 46ab8cd | 2013-10-30 17:07:46 -0500 | [diff] [blame] | 351 | if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { |
| 352 | hda_work_around(dev); |
| 353 | return 0; |
| 354 | } |
| 355 | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 356 | offset = pci_find_capability(dev, PCI_CAP_ID_PM); |
| 357 | |
| 358 | if (offset != 0) { |
| 359 | set_d3hot_bits(dev, offset); |
| 360 | return 0; |
| 361 | } |
| 362 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 363 | /* |
| 364 | * For some reason some of the devices don't have the capability pointer set correctly. |
| 365 | * Work around this by hard coding the offset. |
| 366 | */ |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 367 | switch (dev->path.pci.devfn) { |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 368 | case PCI_DEVFN(MMC_DEV, MMC_FUNC): |
| 369 | offset = 0x80; |
| 370 | break; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 371 | case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): |
| 372 | offset = 0x80; |
| 373 | break; |
| 374 | case PCI_DEVFN(SD_DEV, SD_FUNC): |
| 375 | offset = 0x80; |
| 376 | break; |
Mate Kukri | 45b51e0 | 2020-07-03 14:44:49 +0200 | [diff] [blame] | 377 | case PCI_DEVFN(MMC45_DEV, MMC45_FUNC): |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 378 | offset = 0x80; |
| 379 | break; |
| 380 | case PCI_DEVFN(LPE_DEV, LPE_FUNC): |
| 381 | offset = 0x80; |
| 382 | break; |
| 383 | case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): |
| 384 | offset = 0x80; |
| 385 | break; |
| 386 | case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): |
| 387 | offset = 0x80; |
| 388 | break; |
| 389 | case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): |
| 390 | offset = 0x80; |
| 391 | break; |
| 392 | case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): |
| 393 | offset = 0x80; |
| 394 | break; |
| 395 | case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): |
| 396 | offset = 0x80; |
| 397 | break; |
| 398 | case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): |
| 399 | offset = 0x80; |
| 400 | break; |
| 401 | case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): |
| 402 | offset = 0x80; |
| 403 | break; |
| 404 | case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): |
| 405 | offset = 0x80; |
| 406 | break; |
| 407 | case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): |
| 408 | offset = 0x80; |
| 409 | break; |
| 410 | case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): |
| 411 | offset = 0x80; |
| 412 | break; |
| 413 | case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): |
| 414 | offset = 0x80; |
| 415 | break; |
| 416 | case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): |
| 417 | offset = 0x80; |
| 418 | break; |
| 419 | case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): |
| 420 | offset = 0x80; |
| 421 | break; |
| 422 | case PCI_DEVFN(SPI_DEV, SPI_FUNC): |
| 423 | offset = 0x80; |
| 424 | break; |
| 425 | case PCI_DEVFN(SATA_DEV, SATA_FUNC): |
| 426 | offset = 0x70; |
| 427 | break; |
| 428 | case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): |
| 429 | offset = 0x70; |
| 430 | break; |
| 431 | case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): |
| 432 | offset = 0x70; |
| 433 | break; |
| 434 | case PCI_DEVFN(HDA_DEV, HDA_FUNC): |
| 435 | offset = 0x50; |
| 436 | break; |
| 437 | case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): |
| 438 | offset = 0x50; |
| 439 | break; |
| 440 | case PCI_DEVFN(TXE_DEV, TXE_FUNC): |
Aaron Durbin | 1eae3ee | 2013-10-30 17:08:59 -0500 | [diff] [blame] | 441 | /* TXE cannot be placed in D3Hot. */ |
| 442 | return 0; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 443 | case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): |
| 444 | offset = 0xa0; |
| 445 | break; |
| 446 | case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): |
| 447 | offset = 0xa0; |
| 448 | break; |
| 449 | case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): |
| 450 | offset = 0xa0; |
| 451 | break; |
| 452 | case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): |
| 453 | offset = 0xa0; |
| 454 | break; |
| 455 | } |
| 456 | |
| 457 | if (offset != 0) { |
| 458 | set_d3hot_bits(dev, offset); |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | return -1; |
| 463 | } |
| 464 | |
| 465 | /* Common PCI device function disable. */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame] | 466 | void southcluster_enable_dev(struct device *dev) |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 467 | { |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 468 | uint16_t reg16; |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 469 | |
| 470 | if (!dev->enabled) { |
| 471 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 472 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 473 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 474 | dev_path(dev), slot, func); |
| 475 | |
| 476 | /* Ensure memory, io, and bus master are all disabled */ |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 477 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 478 | reg16 &= ~(PCI_COMMAND_MASTER | |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 479 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 480 | pci_write_config16(dev, PCI_COMMAND, reg16); |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 481 | |
| 482 | /* Place device in D3Hot */ |
| 483 | if (place_device_in_d3hot(dev) < 0) { |
| 484 | printk(BIOS_WARNING, |
| 485 | "Could not place %02x.%01x into D3Hot. " |
| 486 | "Keeping device visible.\n", slot, func); |
| 487 | return; |
| 488 | } |
| 489 | /* Disable this device if possible */ |
| 490 | sc_disable_devfn(dev); |
| 491 | } else { |
| 492 | /* Enable SERR */ |
Elyes HAOUAS | 6468d87d | 2020-04-29 10:22:42 +0200 | [diff] [blame] | 493 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 494 | } |
| 495 | } |
| 496 | |
Furquan Shaikh | 338fd9a | 2020-04-24 22:57:05 -0700 | [diff] [blame] | 497 | static void southcluster_inject_dsdt(const struct device *device) |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 498 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 499 | struct global_nvs *gnvs; |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 500 | |
| 501 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 502 | if (!gnvs) { |
| 503 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); |
| 504 | if (gnvs) |
| 505 | memset(gnvs, 0, sizeof(*gnvs)); |
| 506 | } |
| 507 | |
| 508 | if (gnvs) { |
| 509 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 510 | /* And tell SMI about it */ |
Kyösti Mälkki | c3c5521 | 2020-06-17 10:34:26 +0300 | [diff] [blame] | 511 | apm_control(APM_CNT_GNVS_UPDATE); |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 512 | |
| 513 | /* Add it to DSDT. */ |
| 514 | acpigen_write_scope("\\"); |
| 515 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 516 | acpigen_pop_len(); |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 521 | static struct device_operations device_ops = { |
| 522 | .read_resources = sc_read_resources, |
| 523 | .set_resources = pci_dev_set_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 524 | .acpi_inject_dsdt = southcluster_inject_dsdt, |
Vladimir Serbinenko | 7fb149d | 2014-10-08 22:56:27 +0200 | [diff] [blame] | 525 | .write_acpi_tables = acpi_write_hpet, |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 526 | .init = sc_init, |
Aaron Durbin | d7bc23a | 2013-10-29 16:37:10 -0500 | [diff] [blame] | 527 | .enable = southcluster_enable_dev, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 528 | .scan_bus = scan_static_bus, |
Aaron Durbin | e18d68f | 2013-10-24 00:05:31 -0500 | [diff] [blame] | 529 | .ops_pci = &soc_pci_ops, |
| 530 | }; |
| 531 | |
| 532 | static const struct pci_driver southcluster __pci_driver = { |
| 533 | .ops = &device_ops, |
| 534 | .vendor = PCI_VENDOR_ID_INTEL, |
| 535 | .device = LPC_DEVID, |
| 536 | }; |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 537 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 538 | int __weak mainboard_get_spi_config(struct spi_config *cfg) |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 539 | { |
| 540 | return -1; |
| 541 | } |
| 542 | |
| 543 | static void finalize_chipset(void *unused) |
| 544 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 545 | u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); |
| 546 | u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); |
| 547 | u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); |
| 548 | u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); |
| 549 | u8 *spi = (u8 *)SPI_BASE_ADDRESS; |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 550 | struct spi_config cfg; |
| 551 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 552 | /* Set the lock enable on the BIOS control register */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 553 | write32(bcr, read32(bcr) | BCR_LE); |
| 554 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 555 | /* Set BIOS lock down bit controlling boot block size and swapping */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 556 | write32(gcs, read32(gcs) | BILD); |
| 557 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 558 | /* Lock sleep stretching policy and set SMI lock */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 559 | write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); |
| 560 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 561 | /* Set the CF9 lock */ |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 562 | write32(etr, read32(etr) | CF9LOCK); |
| 563 | |
| 564 | if (mainboard_get_spi_config(&cfg) < 0) { |
| 565 | printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); |
| 566 | } else { |
| 567 | write16(spi + PREOP, cfg.preop); |
| 568 | write16(spi + OPTYPE, cfg.optype); |
| 569 | write32(spi + OPMENU0, cfg.opmenu[0]); |
| 570 | write32(spi + OPMENU1, cfg.opmenu[1]); |
| 571 | write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); |
| 572 | write32(spi + UVSCC, cfg.uvscc); |
| 573 | write32(spi + LVSCC, cfg.lvscc | VCL); |
| 574 | } |
Aaron Durbin | 4177db5 | 2014-02-05 14:55:26 -0600 | [diff] [blame] | 575 | } |
| 576 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 577 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); |
| 578 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); |