Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 3 | config NORTHBRIDGE_INTEL_SANDYBRIDGE |
Vladimir Serbinenko | 309fc4c | 2014-08-24 22:35:29 +0200 | [diff] [blame] | 4 | bool |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 5 | select CACHE_MRC_SETTINGS |
Vladimir Serbinenko | 309fc4c | 2014-08-24 22:35:29 +0200 | [diff] [blame] | 6 | select CPU_INTEL_MODEL_206AX |
| 7 | select HAVE_DEBUG_RAM_SETUP |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 8 | select INTEL_GMA_ACPI |
Vladimir Serbinenko | 309fc4c | 2014-08-24 22:35:29 +0200 | [diff] [blame] | 9 | |
Nico Huber | 772a154 | 2019-05-10 16:48:14 +0200 | [diff] [blame] | 10 | if NORTHBRIDGE_INTEL_SANDYBRIDGE |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 11 | |
Patrick Rudolph | 1ee3dbc | 2020-02-28 13:11:13 +0100 | [diff] [blame] | 12 | config SANDYBRIDGE_VBOOT_IN_ROMSTAGE |
| 13 | bool |
| 14 | default n |
| 15 | help |
| 16 | Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE. |
| 17 | |
| 18 | config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK |
| 19 | depends on VBOOT |
| 20 | depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE |
| 21 | bool "Start verstage in bootblock" |
| 22 | default y |
| 23 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 24 | select VBOOT_SEPARATE_VERSTAGE |
| 25 | help |
| 26 | Sandy Bridge can either start verstage in a separate stage |
| 27 | right after the bootblock has run or it can start it |
| 28 | after romstage for compatibility reasons. |
| 29 | Sandy Bridge however uses a mrc.bin to initialize memory which |
| 30 | needs to be located at a fixed offset. Therefore even with |
| 31 | a separate verstage starting after the bootblock that same |
| 32 | binary is used meaning a jump is made from RW to the RO region |
| 33 | and back to the RW region after the binary is done. |
| 34 | |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 35 | config VBOOT |
Patrick Rudolph | 1ee3dbc | 2020-02-28 13:11:13 +0100 | [diff] [blame] | 36 | select VBOOT_MUST_REQUEST_DISPLAY |
| 37 | select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK |
Julius Werner | 1210b41 | 2017-03-27 19:26:32 -0700 | [diff] [blame] | 38 | |
Vladimir Serbinenko | 144eea0 | 2016-02-10 02:36:04 +0100 | [diff] [blame] | 39 | config USE_NATIVE_RAMINIT |
| 40 | bool "Use native raminit" |
| 41 | default y |
| 42 | help |
| 43 | Select if you want to use coreboot implementation of raminit rather than |
| 44 | System Agent/MRC.bin. You should answer Y. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | |
Patrick Rudolph | b794a69 | 2017-08-08 13:13:51 +0200 | [diff] [blame] | 46 | config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES |
| 47 | bool "Ignore vendor programmed fuses that limit max. DRAM frequency" |
| 48 | default n |
| 49 | depends on USE_NATIVE_RAMINIT |
| 50 | help |
| 51 | Ignore the mainboard's vendor programmed fuses that might limit the |
| 52 | maximum DRAM frequency. By selecting this option the fuses will be |
| 53 | ignored and the only limits on DRAM frequency are set by RAM's SPD and |
| 54 | hard fuses in southbridge's clockgen. |
| 55 | Disabled by default as it might causes system instability. |
| 56 | Handle with care! |
| 57 | |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 58 | config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS |
| 59 | bool "Ignore XMP profile max DIMMs per channel" |
| 60 | default n |
| 61 | depends on USE_NATIVE_RAMINIT |
| 62 | help |
| 63 | Ignore the max DIMMs per channel restriciton defined in XMP profiles. |
| 64 | Disabled by default as it might cause system instability. |
| 65 | Handle with care! |
| 66 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 67 | config CBFS_SIZE |
| 68 | hex |
| 69 | default 0x100000 |
| 70 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 71 | config VGA_BIOS_ID |
| 72 | string |
| 73 | default "8086,0106" |
| 74 | |
Nico Huber | 2b5c021 | 2017-07-29 01:10:49 +0200 | [diff] [blame] | 75 | config MMCONF_BASE_ADDRESS |
| 76 | hex |
Nico Huber | 2b5c021 | 2017-07-29 01:10:49 +0200 | [diff] [blame] | 77 | default 0xf0000000 |
| 78 | help |
Arthur Heymans | 742a0e9 | 2018-01-29 16:34:46 +0100 | [diff] [blame] | 79 | The MRC blob requires it to be at 0xf0000000. |
Nico Huber | 2b5c021 | 2017-07-29 01:10:49 +0200 | [diff] [blame] | 80 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 81 | config DCACHE_RAM_BASE |
| 82 | hex |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 83 | default 0xfefe0000 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 84 | |
Arthur Heymans | 67d59d1 | 2019-11-16 20:06:20 +0100 | [diff] [blame] | 85 | config DCACHE_BSP_STACK_SIZE |
| 86 | hex |
Arthur Heymans | 8d82109 | 2019-11-25 06:56:04 +0100 | [diff] [blame] | 87 | default 0x10000 |
| 88 | help |
| 89 | The amount of BSP stack anticipated in bootblock and |
| 90 | other stages. |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 91 | |
| 92 | if USE_NATIVE_RAMINIT |
| 93 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 94 | config DCACHE_RAM_SIZE |
| 95 | hex |
| 96 | default 0x20000 |
| 97 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 98 | config DCACHE_RAM_MRC_VAR_SIZE |
| 99 | hex |
| 100 | default 0x0 |
| 101 | |
Angel Pons | 09fc4b9 | 2020-11-19 12:02:07 +0100 | [diff] [blame] | 102 | config RAMINIT_ALWAYS_ALLOW_DLL_OFF |
| 103 | bool "Also enable memory DLL-off mode on desktops and servers" |
| 104 | default n |
| 105 | help |
| 106 | If enabled, allow enabling DLL-off mode for platforms other than |
| 107 | mobile. Saves power at the expense of higher exit latencies. Has |
| 108 | no effect on mobile platforms, where DLL-off is always allowed. |
| 109 | Power down is disabled for stability when running at high clocks. |
| 110 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 111 | config RAMINIT_ENABLE_ECC |
| 112 | bool "Enable ECC if supported" |
| 113 | default y |
| 114 | help |
| 115 | Enable ECC if supported by both, host and RAM. |
| 116 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 117 | endif # USE_NATIVE_RAMINIT |
| 118 | |
| 119 | if !USE_NATIVE_RAMINIT |
| 120 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 121 | config DCACHE_RAM_SIZE |
| 122 | hex |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 123 | default 0x17000 |
Kyösti Mälkki | fbdb085 | 2013-07-01 11:21:53 +0300 | [diff] [blame] | 124 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 125 | config DCACHE_RAM_MRC_VAR_SIZE |
| 126 | hex |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 127 | default 0x9000 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 128 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 129 | config MRC_FILE |
| 130 | string "Intel System Agent path and filename" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 131 | default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 132 | help |
| 133 | The path and filename of the file to use as System Agent |
| 134 | binary. |
| 135 | |
Kyösti Mälkki | 9551bed | 2016-07-20 10:49:38 +0300 | [diff] [blame] | 136 | endif # !USE_NATIVE_RAMINIT |
Kyösti Mälkki | 0306e6a | 2016-06-23 12:41:40 +0300 | [diff] [blame] | 137 | |
Nico Huber | 612a867 | 2019-02-19 19:11:29 +0100 | [diff] [blame] | 138 | config INTEL_GMA_BCLV_OFFSET |
| 139 | default 0x48254 |
| 140 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 141 | endif |