Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Matt DeVillier | 6d6fb6b | 2020-02-26 12:55:49 -0600 | [diff] [blame] | 3 | # Enable Panel as eDP and configure power delays |
Michael Niewöhner | 97e21d3 | 2020-12-28 00:49:33 +0100 | [diff] [blame] | 4 | register "panel_cfg" = "{ |
| 5 | .up_delay_ms = 210, // T3 |
| 6 | .down_delay_ms = 500, // T10 |
| 7 | .cycle_delay_ms = 5000, // T12 |
| 8 | .backlight_on_delay_ms = 1, // T7 |
| 9 | .backlight_off_delay_ms = 200, // T9 |
| 10 | }" |
Matt DeVillier | 6d6fb6b | 2020-02-26 12:55:49 -0600 | [diff] [blame] | 11 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 12 | # Enable deep Sx states |
| 13 | register "deep_s3_enable_ac" = "1" |
| 14 | register "deep_s3_enable_dc" = "1" |
| 15 | register "deep_s5_enable_ac" = "1" |
| 16 | register "deep_s5_enable_dc" = "1" |
| 17 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 18 | |
| 19 | register "eist_enable" = "1" |
| 20 | |
| 21 | # GPE configuration |
| 22 | # Note that GPE events called out in ASL code rely on this |
| 23 | # route. i.e. If this route changes then the affected GPE |
| 24 | # offset bits also need to be changed. |
| 25 | register "gpe0_dw0" = "GPP_C" |
| 26 | register "gpe0_dw1" = "GPP_D" |
| 27 | register "gpe0_dw2" = "GPP_E" |
| 28 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 29 | # Disable DPTF |
| 30 | register "dptf_enable" = "0" |
| 31 | |
| 32 | # FSP Configuration |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 33 | register "SataSalpSupport" = "1" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 34 | |
| 35 | # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 |
| 36 | register "SataPortsEnable[0]" = "1" |
| 37 | register "SataPortsEnable[1]" = "1" |
| 38 | register "SataPortsEnable[2]" = "1" |
| 39 | register "SataPortsDevSlp[0]" = "1" |
| 40 | register "SataPortsDevSlp[1]" = "1" |
| 41 | register "SataPortsDevSlp[2]" = "1" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 42 | register "DspEnable" = "0" |
| 43 | register "IoBufferOwnership" = "0" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 44 | register "SkipExtGfxScan" = "1" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 45 | register "SaGv" = "SaGv_Enabled" |
| 46 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 47 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 48 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 49 | register "PmConfigSlpAMinAssert" = "3" # 2s |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 50 | |
| 51 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 52 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 53 | # Enable Root Ports 3, 4 and 9 |
| 54 | register "PcieRpEnable[2]" = "1" # Ethernet controller |
| 55 | register "PcieRpClkReqSupport[2]" = "1" |
| 56 | register "PcieRpClkReqNumber[2]" = "0" |
| 57 | register "PcieRpClkSrcNumber[2]" = "0" |
| 58 | register "PcieRpAdvancedErrorReporting[2]" = "1" |
| 59 | register "PcieRpLtrEnable[2]" = "1" |
| 60 | |
| 61 | register "PcieRpEnable[3]" = "1" # Wireless controller |
| 62 | register "PcieRpClkReqSupport[3]" = "1" |
| 63 | register "PcieRpClkReqNumber[3]" = "1" |
| 64 | register "PcieRpClkSrcNumber[3]" = "1" |
| 65 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 66 | register "PcieRpLtrEnable[3]" = "1" |
| 67 | |
| 68 | register "PcieRpEnable[8]" = "1" # NVMe controller |
Matt DeVillier | 75afc79 | 2020-02-26 13:06:01 -0600 | [diff] [blame] | 69 | register "PcieRpClkReqSupport[8]" = "1" |
| 70 | register "PcieRpClkReqNumber[8]" = "4" |
| 71 | register "PcieRpClkSrcNumber[8]" = "4" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 72 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 73 | register "PcieRpLtrEnable[8]" = "1" |
| 74 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 75 | |
| 76 | # PL1 override 25W |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 77 | # PL2 override 44W |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 78 | register "power_limits_config" = "{ |
| 79 | .tdp_pl1_override = 25, |
| 80 | .tdp_pl2_override = 44, |
| 81 | }" |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 82 | |
| 83 | # Send an extra VR mailbox command for the PS4 exit issue |
| 84 | register "SendVrMbxCmd" = "2" |
| 85 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 86 | device domain 0 on |
Felix Singer | 9e345c8 | 2023-10-23 06:43:05 +0200 | [diff] [blame] | 87 | device ref igpu on end |
| 88 | device ref sa_thermal on end |
Felix Singer | 6c83a71 | 2024-06-23 00:25:18 +0200 | [diff] [blame] | 89 | device ref south_xhci on |
| 90 | register "usb2_ports" = "{ |
| 91 | [0] = USB2_PORT_MID(OC1), // Type-A Port (left) |
| 92 | [1] = USB2_PORT_MID(OC1), // Type-A Port (left) |
| 93 | [2] = USB2_PORT_FLEX(OC_SKIP), // FPR |
| 94 | [3] = USB2_PORT_FLEX(OC_SKIP), // SD |
| 95 | [4] = USB2_PORT_FLEX(OC_SKIP), // INT |
| 96 | [5] = USB2_PORT_MID(OC1), // Type-A Port (right) |
| 97 | [6] = USB2_PORT_FLEX(OC_SKIP), // Webcam |
| 98 | [7] = USB2_PORT_MID(OC_SKIP), // mPCIe / WiFi Port |
| 99 | [8] = USB2_PORT_MID(OC_SKIP), // mSATA / WWAN Port |
| 100 | }" |
| 101 | |
| 102 | register "usb3_ports" = "{ |
| 103 | [0] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left) |
| 104 | [1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left) |
| 105 | }" |
| 106 | end |
Felix Singer | 9e345c8 | 2023-10-23 06:43:05 +0200 | [diff] [blame] | 107 | device ref thermal on end |
| 108 | device ref heci1 on end |
| 109 | device ref sata on end |
| 110 | device ref pcie_rp3 on end |
| 111 | device ref pcie_rp4 on end |
| 112 | device ref pcie_rp9 on end |
| 113 | device ref lpc_espi on |
Felix Singer | dcddc53f | 2024-06-23 03:39:24 +0200 | [diff] [blame^] | 114 | register "gen1_dec" = "0x000c0681" |
| 115 | register "gen2_dec" = "0x000c1641" |
| 116 | |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 117 | chip ec/51nb/npce985la0dx |
| 118 | device pnp 0c09.0 on end |
| 119 | device pnp 4e.5 on end |
| 120 | device pnp 4e.6 on end |
| 121 | device pnp 4e.11 on end |
| 122 | end |
Felix Singer | 9e345c8 | 2023-10-23 06:43:05 +0200 | [diff] [blame] | 123 | end |
| 124 | device ref pmc on end |
| 125 | device ref hda on end |
| 126 | device ref smbus on end |
Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame] | 127 | end |
| 128 | end |