skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 17a5f75..51cb89a 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -75,18 +75,6 @@
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
- register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
- register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left)
- register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR
- register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
- register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT
- register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
- register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port
-
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
# PL1 override 25W
# PL2 override 44W
@@ -101,7 +89,24 @@
device domain 0 on
device ref igpu on end
device ref sa_thermal on end
- device ref south_xhci on end
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC1), // Type-A Port (left)
+ [1] = USB2_PORT_MID(OC1), // Type-A Port (left)
+ [2] = USB2_PORT_FLEX(OC_SKIP), // FPR
+ [3] = USB2_PORT_FLEX(OC_SKIP), // SD
+ [4] = USB2_PORT_FLEX(OC_SKIP), // INT
+ [5] = USB2_PORT_MID(OC1), // Type-A Port (right)
+ [6] = USB2_PORT_FLEX(OC_SKIP), // Webcam
+ [7] = USB2_PORT_MID(OC_SKIP), // mPCIe / WiFi Port
+ [8] = USB2_PORT_MID(OC_SKIP), // mSATA / WWAN Port
+ }"
+
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left)
+ [1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (left)
+ }"
+ end
device ref thermal on end
device ref heci1 on end
device ref sata on end