Matthew Garrett | 2f62a35 | 2018-07-24 14:06:39 -0700 | [diff] [blame^] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # Enable deep Sx states |
| 4 | register "deep_s3_enable_ac" = "1" |
| 5 | register "deep_s3_enable_dc" = "1" |
| 6 | register "deep_s5_enable_ac" = "1" |
| 7 | register "deep_s5_enable_dc" = "1" |
| 8 | register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| 9 | |
| 10 | register "eist_enable" = "1" |
| 11 | |
| 12 | # GPE configuration |
| 13 | # Note that GPE events called out in ASL code rely on this |
| 14 | # route. i.e. If this route changes then the affected GPE |
| 15 | # offset bits also need to be changed. |
| 16 | register "gpe0_dw0" = "GPP_C" |
| 17 | register "gpe0_dw1" = "GPP_D" |
| 18 | register "gpe0_dw2" = "GPP_E" |
| 19 | |
| 20 | register "gen1_dec" = "0x000c0081" |
| 21 | register "gen2_dec" = "0x000c0681" |
| 22 | register "gen3_dec" = "0x000c1641" |
| 23 | |
| 24 | # Enable "Intel Speed Shift Technology" |
| 25 | register "speed_shift_enable" = "1" |
| 26 | |
| 27 | # Disable DPTF |
| 28 | register "dptf_enable" = "0" |
| 29 | |
| 30 | # FSP Configuration |
| 31 | register "ProbelessTrace" = "0" |
| 32 | register "EnableLan" = "0" |
| 33 | register "EnableSata" = "1" |
| 34 | register "SataSalpSupport" = "1" |
| 35 | register "SataMode" = "0" |
| 36 | |
| 37 | # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 |
| 38 | register "SataPortsEnable[0]" = "1" |
| 39 | register "SataPortsEnable[1]" = "1" |
| 40 | register "SataPortsEnable[2]" = "1" |
| 41 | register "SataPortsDevSlp[0]" = "1" |
| 42 | register "SataPortsDevSlp[1]" = "1" |
| 43 | register "SataPortsDevSlp[2]" = "1" |
| 44 | register "SataPwrOptEnable" = "1" |
| 45 | register "EnableAzalia" = "1" |
| 46 | register "DspEnable" = "0" |
| 47 | register "IoBufferOwnership" = "0" |
| 48 | register "EnableTraceHub" = "0" |
| 49 | register "SsicPortEnable" = "0" |
| 50 | register "SmbusEnable" = "1" |
| 51 | register "Cio2Enable" = "0" |
| 52 | register "ScsEmmcEnabled" = "0" |
| 53 | register "ScsEmmcHs400Enabled" = "0" |
| 54 | register "ScsSdCardEnabled" = "0" |
| 55 | register "PttSwitch" = "0" |
| 56 | register "SkipExtGfxScan" = "1" |
| 57 | register "Device4Enable" = "1" |
| 58 | register "HeciEnabled" = "1" |
| 59 | register "SaGv" = "SaGv_Enabled" |
| 60 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 61 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 62 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 63 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 64 | register "PmTimerDisabled" = "0" |
| 65 | |
| 66 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 67 | |
| 68 | register "pirqa_routing" = "PCH_IRQ11" |
| 69 | register "pirqb_routing" = "PCH_IRQ10" |
| 70 | register "pirqc_routing" = "PCH_IRQ11" |
| 71 | register "pirqd_routing" = "PCH_IRQ11" |
| 72 | register "pirqe_routing" = "PCH_IRQ11" |
| 73 | register "pirqf_routing" = "PCH_IRQ11" |
| 74 | register "pirqg_routing" = "PCH_IRQ11" |
| 75 | register "pirqh_routing" = "PCH_IRQ11" |
| 76 | |
| 77 | register "PmConfigPciClockRun" = "1" |
| 78 | |
| 79 | # Enable Root Ports 3, 4 and 9 |
| 80 | register "PcieRpEnable[2]" = "1" # Ethernet controller |
| 81 | register "PcieRpClkReqSupport[2]" = "1" |
| 82 | register "PcieRpClkReqNumber[2]" = "0" |
| 83 | register "PcieRpClkSrcNumber[2]" = "0" |
| 84 | register "PcieRpAdvancedErrorReporting[2]" = "1" |
| 85 | register "PcieRpLtrEnable[2]" = "1" |
| 86 | |
| 87 | register "PcieRpEnable[3]" = "1" # Wireless controller |
| 88 | register "PcieRpClkReqSupport[3]" = "1" |
| 89 | register "PcieRpClkReqNumber[3]" = "1" |
| 90 | register "PcieRpClkSrcNumber[3]" = "1" |
| 91 | register "PcieRpAdvancedErrorReporting[3]" = "1" |
| 92 | register "PcieRpLtrEnable[3]" = "1" |
| 93 | |
| 94 | register "PcieRpEnable[8]" = "1" # NVMe controller |
| 95 | register "PcieRpClkReqSupport[8]" = "0" |
| 96 | register "PcieRpClkReqNumber[8]" = "2" |
| 97 | register "PcieRpClkSrcNumber[8]" = "2" |
| 98 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 99 | register "PcieRpLtrEnable[8]" = "1" |
| 100 | |
| 101 | register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| 102 | register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| 103 | register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
| 104 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Webcam |
| 105 | register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB |
| 106 | |
| 107 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
| 108 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
| 109 | register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) |
| 110 | |
| 111 | # PL1 override 25W |
| 112 | register "tdp_pl1_override" = "25" |
| 113 | |
| 114 | # PL2 override 44W |
| 115 | register "tdp_pl2_override" = "44" |
| 116 | |
| 117 | # Send an extra VR mailbox command for the PS4 exit issue |
| 118 | register "SendVrMbxCmd" = "2" |
| 119 | |
| 120 | # Lock Down |
| 121 | register "common_soc_config" = "{ |
| 122 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 123 | }" |
| 124 | |
| 125 | device cpu_cluster 0 on |
| 126 | device lapic 0 on end |
| 127 | end |
| 128 | device domain 0 on |
| 129 | device pci 00.0 on end # Host Bridge |
| 130 | device pci 02.0 on end # Integrated Graphics Device |
| 131 | device pci 14.0 on end # USB xHCI |
| 132 | device pci 14.1 off end # USB xDCI (OTG) |
| 133 | device pci 14.2 on end # Thermal Subsystem |
| 134 | device pci 16.0 on end # Management Engine Interface 1 |
| 135 | device pci 16.1 off end # Management Engine Interface 2 |
| 136 | device pci 16.2 off end # Management Engine IDE-R |
| 137 | device pci 16.3 off end # Management Engine KT Redirection |
| 138 | device pci 16.4 off end # Management Engine Interface 3 |
| 139 | device pci 17.0 on end # SATA |
| 140 | device pci 1c.0 off end # PCI Express Port 1 |
| 141 | device pci 1c.1 off end # PCI Express Port 2 |
| 142 | device pci 1c.2 on end # PCI Express Port 3 |
| 143 | device pci 1c.3 on end # PCI Express Port 4 |
| 144 | device pci 1c.4 off end # PCI Express Port 5 |
| 145 | device pci 1c.5 off end # PCI Express Port 6 |
| 146 | device pci 1c.6 off end # PCI Express Port 7 |
| 147 | device pci 1c.7 off end # PCI Express Port 8 |
| 148 | device pci 1d.0 on end # PCI Express Port 9 |
| 149 | device pci 1d.1 off end # PCI Express Port 10 |
| 150 | device pci 1d.2 off end # PCI Express Port 11 |
| 151 | device pci 1d.3 off end # PCI Express Port 12 |
| 152 | device pci 1f.0 on |
| 153 | chip ec/51nb/npce985la0dx |
| 154 | device pnp 0c09.0 on end |
| 155 | device pnp 4e.5 on end |
| 156 | device pnp 4e.6 on end |
| 157 | device pnp 4e.11 on end |
| 158 | end |
| 159 | end # LPC Interface |
| 160 | device pci 1f.1 off end # P2SB |
| 161 | device pci 1f.2 on end # Power Management Controller |
| 162 | device pci 1f.3 on end # Intel HDA |
| 163 | device pci 1f.4 on end # SMBus |
| 164 | device pci 1f.5 off end # PCH SPI |
| 165 | device pci 1f.6 off end # GbE |
| 166 | end |
| 167 | end |