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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# SPDX-License-Identifier: GPL-2.0-only
Patrick Georgi0588d192009-08-12 15:00:51 +00002
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02003config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +00004 bool
Jens Rottmann0d11f2d2010-08-26 12:46:02 +00005 select HAVE_DEBUG_RAM_SETUP
Paul Menzelea8f3b42014-09-21 12:21:36 +02006 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01007 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +01008 select INTEL_GMA_SSC_ALTERNATE_REF
Patrick Rudolph46cf5c22017-04-03 19:09:45 +02009 select INTEL_EDID
Nico Huberce642f02017-05-19 15:08:21 +020010 select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
Elyes Haouase8457532022-10-30 06:46:05 +010011 select NO_DDR5
12 select NO_LPDDR4
13 select NO_DDR4
14 select NO_DDR3
15 select USE_DDR2
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000016
Elyes Haouasd2ebc4d2023-01-02 15:28:41 +010017if NORTHBRIDGE_INTEL_I945
18
Arthur Heymans48d5b8d2020-04-09 11:44:37 +020019config VBOOT
20 select VBOOT_STARTS_IN_BOOTBLOCK
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020021config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
22 def_bool n
23config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
24 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000025
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000026config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000027 string
Arthur Heymansa6b0fc92016-10-16 17:20:35 +020028 default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
29 default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
Patrick Georgi77d66832010-10-01 08:02:45 +000030
Nico Huber7971582e2017-05-20 01:07:48 +020031config I945_LVDS
32 def_bool n
33 select MAINBOARD_HAS_NATIVE_VGA_INIT
34 select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
35 help
36 Selected by mainboards that use native graphics initialization
37 for the LVDS port. A linear framebuffer is only supported for
38 LVDS.
39
Shelley Chen4e9bb332021-10-20 15:43:45 -070040config ECAM_MMCONF_BASE_ADDRESS
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020041 default 0xf0000000
42
Shelley Chen4e9bb332021-10-20 15:43:45 -070043config ECAM_MMCONF_BUS_NUMBER
Angel Ponsa6b09222021-01-20 13:00:02 +010044 int
45 default 64
46
Patrick Georgi77d66832010-10-01 08:02:45 +000047config OVERRIDE_CLOCK_DISABLE
48 bool
49 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000050 help
51 Usually system firmware turns off system memory clock
52 signals to unused SO-DIMM slots to reduce EMI and power
53 consumption.
54 However, some boards do not like unused clock signals to
55 be disabled.
56
57config MAXIMUM_SUPPORTED_FREQUENCY
58 int
59 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000060 help
61 If non-zero, this designates the maximum DDR frequency
62 the board supports, despite what the chipset should be
63 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000064
Peter Stuge751508a2012-01-27 22:17:09 +010065config CHECK_SLFRCS_ON_RESUME
66 def_bool n
67 help
Martin Roth50863da2021-10-01 14:37:30 -060068 On some boards it may be necessary to hard reset early
Peter Stuge751508a2012-01-27 22:17:09 +010069 during resume from S3 if the SLFRCS register indicates that
70 a memory channel is not guaranteed to be in self-refresh.
71 On other boards the check always creates a false positive,
72 effectively making it impossible to resume.
73
Arthur Heymansdce39272018-04-10 16:08:27 +020074config SMM_RESERVED_SIZE
75 hex
76 default 0x100000
77
Angel Ponsf3973bd2020-05-29 01:17:16 +020078config MAX_CPUS
79 int
80 default 4
81
Angel Pons4299cb42021-01-20 12:32:22 +010082config FIXED_MCHBAR_MMIO_BASE
83 default 0xfed14000
84
85config FIXED_DMIBAR_MMIO_BASE
86 default 0xfed18000
87
88config FIXED_EPBAR_MMIO_BASE
89 default 0xfed19000
90
Peter Stugee4bc0f62010-10-01 09:13:18 +000091endif