| Uwe Hermann | c70e9fc | 2010-02-15 23:10:19 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2009 coresystems GmbH |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 19 | |
| Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame^] | 20 | config NORTHBRIDGE_INTEL_I945GC |
| Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 21 | bool |
| Jens Rottmann | 0d11f2d | 2010-08-26 12:46:02 +0000 | [diff] [blame] | 22 | select HAVE_DEBUG_RAM_SETUP |
| Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 23 | |
| Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame^] | 24 | config NORTHBRIDGE_INTEL_I945GM |
| 25 | bool |
| 26 | select HAVE_DEBUG_RAM_SETUP |
| 27 | |
| 28 | if NORTHBRIDGE_INTEL_I945GC || NORTHBRIDGE_INTEL_I945GM |
| 29 | |
| Uwe Hermann | 81b3c0a | 2009-10-30 12:56:59 +0000 | [diff] [blame] | 30 | config FALLBACK_VGA_BIOS_ID |
| 31 | string |
| 32 | default "8086,27a2" |
| Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 33 | |
| 34 | config CHANNEL_XOR_RANDOMIZATION |
| 35 | bool |
| 36 | default n |
| Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 37 | |
| 38 | config OVERRIDE_CLOCK_DISABLE |
| 39 | bool |
| 40 | default n |
| Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 41 | help |
| 42 | Usually system firmware turns off system memory clock |
| 43 | signals to unused SO-DIMM slots to reduce EMI and power |
| 44 | consumption. |
| 45 | However, some boards do not like unused clock signals to |
| 46 | be disabled. |
| 47 | |
| 48 | config MAXIMUM_SUPPORTED_FREQUENCY |
| 49 | int |
| 50 | default 0 |
| Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 51 | help |
| 52 | If non-zero, this designates the maximum DDR frequency |
| 53 | the board supports, despite what the chipset should be |
| 54 | capable of. |
| Peter Stuge | e4bc0f6 | 2010-10-01 09:13:18 +0000 | [diff] [blame^] | 55 | |
| 56 | endif |