blob: b17dda6901eaa74f11c15f1fe4767575debf4c31 [file] [log] [blame]
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010017## Foundation, Inc.
Uwe Hermannc70e9fc2010-02-15 23:10:19 +000018##
Patrick Georgi0588d192009-08-12 15:00:51 +000019
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020020config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +000021 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020022
23if NORTHBRIDGE_INTEL_I945
24
25config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
26 def_bool y
Kyösti Mälkki032c23d2013-07-01 11:21:53 +030027 select MMCONF_SUPPORT
28 select MMCONF_SUPPORT_DEFAULT
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000029 select HAVE_DEBUG_RAM_SETUP
Denis 'GNUtoo' Cariklifd39ddd2013-06-04 04:48:11 +020030 select LAPIC_MONOTONIC_TIMER
Paul Menzelea8f3b42014-09-21 12:21:36 +020031 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010032 select INTEL_GMA_ACPI
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000033
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020034config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
35 def_bool n
36config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
37 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000038
Kyösti Mälkki032c23d2013-07-01 11:21:53 +030039config BOOTBLOCK_NORTHBRIDGE_INIT
40 string
41 default "northbridge/intel/i945/bootblock.c"
42
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000043config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000044 string
45 default "8086,27a2"
Patrick Georgi77d66832010-10-01 08:02:45 +000046
47config CHANNEL_XOR_RANDOMIZATION
48 bool
49 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000050
51config OVERRIDE_CLOCK_DISABLE
52 bool
53 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000054 help
55 Usually system firmware turns off system memory clock
56 signals to unused SO-DIMM slots to reduce EMI and power
57 consumption.
58 However, some boards do not like unused clock signals to
59 be disabled.
60
61config MAXIMUM_SUPPORTED_FREQUENCY
62 int
63 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000064 help
65 If non-zero, this designates the maximum DDR frequency
66 the board supports, despite what the chipset should be
67 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000068
Peter Stuge751508a2012-01-27 22:17:09 +010069config CHECK_SLFRCS_ON_RESUME
70 def_bool n
71 help
72 On some boards it may be neccessary to hard reset early
73 during resume from S3 if the SLFRCS register indicates that
74 a memory channel is not guaranteed to be in self-refresh.
75 On other boards the check always creates a false positive,
76 effectively making it impossible to resume.
77
Peter Stugee4bc0f62010-10-01 09:13:18 +000078endif