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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# SPDX-License-Identifier: GPL-2.0-only
Patrick Georgi0588d192009-08-12 15:00:51 +00002
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02003config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +00004 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02005
6if NORTHBRIDGE_INTEL_I945
7
Elyes HAOUAS00b5f532021-02-01 09:45:08 +01008config NORTHBRIDGE_SPECIFIC_OPTIONS
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02009 def_bool y
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000010 select HAVE_DEBUG_RAM_SETUP
Paul Menzelea8f3b42014-09-21 12:21:36 +020011 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010012 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +010013 select INTEL_GMA_SSC_ALTERNATE_REF
Patrick Rudolph46cf5c22017-04-03 19:09:45 +020014 select INTEL_EDID
Nico Huberce642f02017-05-19 15:08:21 +020015 select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000016
Arthur Heymans48d5b8d2020-04-09 11:44:37 +020017config VBOOT
18 select VBOOT_STARTS_IN_BOOTBLOCK
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020019config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
20 def_bool n
21config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
22 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000023
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000024config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000025 string
Arthur Heymansa6b0fc92016-10-16 17:20:35 +020026 default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
27 default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
Patrick Georgi77d66832010-10-01 08:02:45 +000028
Nico Huber7971582e2017-05-20 01:07:48 +020029config I945_LVDS
30 def_bool n
31 select MAINBOARD_HAS_NATIVE_VGA_INIT
32 select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
33 help
34 Selected by mainboards that use native graphics initialization
35 for the LVDS port. A linear framebuffer is only supported for
36 LVDS.
37
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020038config MMCONF_BASE_ADDRESS
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020039 default 0xf0000000
40
Angel Ponsa6b09222021-01-20 13:00:02 +010041config MMCONF_BUS_NUMBER
42 int
43 default 64
44
Patrick Georgi77d66832010-10-01 08:02:45 +000045config OVERRIDE_CLOCK_DISABLE
46 bool
47 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000048 help
49 Usually system firmware turns off system memory clock
50 signals to unused SO-DIMM slots to reduce EMI and power
51 consumption.
52 However, some boards do not like unused clock signals to
53 be disabled.
54
55config MAXIMUM_SUPPORTED_FREQUENCY
56 int
57 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000058 help
59 If non-zero, this designates the maximum DDR frequency
60 the board supports, despite what the chipset should be
61 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000062
Peter Stuge751508a2012-01-27 22:17:09 +010063config CHECK_SLFRCS_ON_RESUME
64 def_bool n
65 help
Martin Roth50863da2021-10-01 14:37:30 -060066 On some boards it may be necessary to hard reset early
Peter Stuge751508a2012-01-27 22:17:09 +010067 during resume from S3 if the SLFRCS register indicates that
68 a memory channel is not guaranteed to be in self-refresh.
69 On other boards the check always creates a false positive,
70 effectively making it impossible to resume.
71
Arthur Heymansdce39272018-04-10 16:08:27 +020072config SMM_RESERVED_SIZE
73 hex
74 default 0x100000
75
Angel Ponsf3973bd2020-05-29 01:17:16 +020076config MAX_CPUS
77 int
78 default 4
79
Angel Pons4299cb42021-01-20 12:32:22 +010080config FIXED_MCHBAR_MMIO_BASE
81 default 0xfed14000
82
83config FIXED_DMIBAR_MMIO_BASE
84 default 0xfed18000
85
86config FIXED_EPBAR_MMIO_BASE
87 default 0xfed19000
88
Peter Stugee4bc0f62010-10-01 09:13:18 +000089endif