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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# SPDX-License-Identifier: GPL-2.0-only
Patrick Georgi0588d192009-08-12 15:00:51 +00002
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02003config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +00004 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02005
6if NORTHBRIDGE_INTEL_I945
7
Elyes HAOUAS00b5f532021-02-01 09:45:08 +01008config NORTHBRIDGE_SPECIFIC_OPTIONS
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02009 def_bool y
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000010 select HAVE_DEBUG_RAM_SETUP
Paul Menzelea8f3b42014-09-21 12:21:36 +020011 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010012 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +010013 select INTEL_GMA_SSC_ALTERNATE_REF
Patrick Rudolph46cf5c22017-04-03 19:09:45 +020014 select INTEL_EDID
Nico Huberce642f02017-05-19 15:08:21 +020015 select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
Elyes Haouase8457532022-10-30 06:46:05 +010016 select NO_DDR5
17 select NO_LPDDR4
18 select NO_DDR4
19 select NO_DDR3
20 select USE_DDR2
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000021
Arthur Heymans48d5b8d2020-04-09 11:44:37 +020022config VBOOT
23 select VBOOT_STARTS_IN_BOOTBLOCK
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020024config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
25 def_bool n
26config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
27 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000028
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000029config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000030 string
Arthur Heymansa6b0fc92016-10-16 17:20:35 +020031 default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
32 default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
Patrick Georgi77d66832010-10-01 08:02:45 +000033
Nico Huber7971582e2017-05-20 01:07:48 +020034config I945_LVDS
35 def_bool n
36 select MAINBOARD_HAS_NATIVE_VGA_INIT
37 select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
38 help
39 Selected by mainboards that use native graphics initialization
40 for the LVDS port. A linear framebuffer is only supported for
41 LVDS.
42
Shelley Chen4e9bb332021-10-20 15:43:45 -070043config ECAM_MMCONF_BASE_ADDRESS
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020044 default 0xf0000000
45
Shelley Chen4e9bb332021-10-20 15:43:45 -070046config ECAM_MMCONF_BUS_NUMBER
Angel Ponsa6b09222021-01-20 13:00:02 +010047 int
48 default 64
49
Patrick Georgi77d66832010-10-01 08:02:45 +000050config OVERRIDE_CLOCK_DISABLE
51 bool
52 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000053 help
54 Usually system firmware turns off system memory clock
55 signals to unused SO-DIMM slots to reduce EMI and power
56 consumption.
57 However, some boards do not like unused clock signals to
58 be disabled.
59
60config MAXIMUM_SUPPORTED_FREQUENCY
61 int
62 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000063 help
64 If non-zero, this designates the maximum DDR frequency
65 the board supports, despite what the chipset should be
66 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000067
Peter Stuge751508a2012-01-27 22:17:09 +010068config CHECK_SLFRCS_ON_RESUME
69 def_bool n
70 help
Martin Roth50863da2021-10-01 14:37:30 -060071 On some boards it may be necessary to hard reset early
Peter Stuge751508a2012-01-27 22:17:09 +010072 during resume from S3 if the SLFRCS register indicates that
73 a memory channel is not guaranteed to be in self-refresh.
74 On other boards the check always creates a false positive,
75 effectively making it impossible to resume.
76
Arthur Heymansdce39272018-04-10 16:08:27 +020077config SMM_RESERVED_SIZE
78 hex
79 default 0x100000
80
Angel Ponsf3973bd2020-05-29 01:17:16 +020081config MAX_CPUS
82 int
83 default 4
84
Angel Pons4299cb42021-01-20 12:32:22 +010085config FIXED_MCHBAR_MMIO_BASE
86 default 0xfed14000
87
88config FIXED_DMIBAR_MMIO_BASE
89 default 0xfed18000
90
91config FIXED_EPBAR_MMIO_BASE
92 default 0xfed19000
93
Peter Stugee4bc0f62010-10-01 09:13:18 +000094endif