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Elyes HAOUAS36787b02020-05-07 12:07:24 +02001# SPDX-License-Identifier: GPL-2.0-only
Patrick Georgi0588d192009-08-12 15:00:51 +00002
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02003config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +00004 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02005
6if NORTHBRIDGE_INTEL_I945
7
Elyes HAOUAS00b5f532021-02-01 09:45:08 +01008config NORTHBRIDGE_SPECIFIC_OPTIONS
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +02009 def_bool y
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000010 select HAVE_DEBUG_RAM_SETUP
Paul Menzelea8f3b42014-09-21 12:21:36 +020011 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010012 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +010013 select INTEL_GMA_SSC_ALTERNATE_REF
Patrick Rudolph46cf5c22017-04-03 19:09:45 +020014 select INTEL_EDID
Nico Huberce642f02017-05-19 15:08:21 +020015 select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
Arthur Heymansf2669322018-04-10 15:15:05 +020016 select PARALLEL_MP
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000017
Arthur Heymans48d5b8d2020-04-09 11:44:37 +020018config VBOOT
19 select VBOOT_STARTS_IN_BOOTBLOCK
20 select VBOOT_SEPARATE_VERSTAGE
21
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020022config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
23 def_bool n
24config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
25 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000026
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000027config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000028 string
Arthur Heymansa6b0fc92016-10-16 17:20:35 +020029 default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
30 default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
Patrick Georgi77d66832010-10-01 08:02:45 +000031
Nico Huber7971582e2017-05-20 01:07:48 +020032config I945_LVDS
33 def_bool n
34 select MAINBOARD_HAS_NATIVE_VGA_INIT
35 select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
36 help
37 Selected by mainboards that use native graphics initialization
38 for the LVDS port. A linear framebuffer is only supported for
39 LVDS.
40
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020041config MMCONF_BASE_ADDRESS
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020042 default 0xf0000000
43
Angel Ponsa6b09222021-01-20 13:00:02 +010044config MMCONF_BUS_NUMBER
45 int
46 default 64
47
Patrick Georgi77d66832010-10-01 08:02:45 +000048config OVERRIDE_CLOCK_DISABLE
49 bool
50 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000051 help
52 Usually system firmware turns off system memory clock
53 signals to unused SO-DIMM slots to reduce EMI and power
54 consumption.
55 However, some boards do not like unused clock signals to
56 be disabled.
57
58config MAXIMUM_SUPPORTED_FREQUENCY
59 int
60 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000061 help
62 If non-zero, this designates the maximum DDR frequency
63 the board supports, despite what the chipset should be
64 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000065
Peter Stuge751508a2012-01-27 22:17:09 +010066config CHECK_SLFRCS_ON_RESUME
67 def_bool n
68 help
69 On some boards it may be neccessary to hard reset early
70 during resume from S3 if the SLFRCS register indicates that
71 a memory channel is not guaranteed to be in self-refresh.
72 On other boards the check always creates a false positive,
73 effectively making it impossible to resume.
74
Arthur Heymansdce39272018-04-10 16:08:27 +020075config SMM_RESERVED_SIZE
76 hex
77 default 0x100000
78
Angel Ponsf3973bd2020-05-29 01:17:16 +020079config MAX_CPUS
80 int
81 default 4
82
Angel Pons4299cb42021-01-20 12:32:22 +010083config FIXED_MCHBAR_MMIO_BASE
84 default 0xfed14000
85
86config FIXED_DMIBAR_MMIO_BASE
87 default 0xfed18000
88
89config FIXED_EPBAR_MMIO_BASE
90 default 0xfed19000
91
Peter Stugee4bc0f62010-10-01 09:13:18 +000092endif