Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | df128a5 | 2019-09-21 18:35:37 +0300 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Arthur Heymans | 742df5a | 2019-06-03 16:24:41 +0200 | [diff] [blame] | 9 | #include "chip.h" |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 10 | #include "i82801gx.h" |
| 11 | |
| 12 | /* Low Power variant has 6 root ports. */ |
| 13 | #define NUM_ROOT_PORTS 6 |
| 14 | |
| 15 | struct root_port_config { |
| 16 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 17 | u32 orig_rpfn; |
| 18 | u32 new_rpfn; |
| 19 | int num_ports; |
| 20 | struct device *ports[NUM_ROOT_PORTS]; |
| 21 | }; |
| 22 | |
| 23 | static struct root_port_config rpc; |
| 24 | |
| 25 | static inline int root_port_is_first(struct device *dev) |
| 26 | { |
| 27 | return PCI_FUNC(dev->path.pci.devfn) == 0; |
| 28 | } |
| 29 | |
| 30 | static inline int root_port_is_last(struct device *dev) |
| 31 | { |
| 32 | return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); |
| 33 | } |
| 34 | |
| 35 | /* Root ports are numbered 1..N in the documentation. */ |
| 36 | static inline int root_port_number(struct device *dev) |
| 37 | { |
| 38 | return PCI_FUNC(dev->path.pci.devfn) + 1; |
| 39 | } |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 40 | |
| 41 | static void pci_init(struct device *dev) |
| 42 | { |
| 43 | u16 reg16; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 44 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 45 | printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 46 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 47 | /* Enable Bus Master */ |
Elyes HAOUAS | 1234925 | 2020-04-27 05:08:26 +0200 | [diff] [blame] | 48 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 49 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 50 | /* Set Cache Line Size to 0x10 */ |
| 51 | // This has no effect but the OS might expect it |
Elyes HAOUAS | ae22fe2 | 2020-05-21 09:04:16 +0200 | [diff] [blame] | 52 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 53 | |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 54 | pci_and_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 55 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 56 | /* Enable IO xAPIC on this PCIe port */ |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 57 | pci_or_config32(dev, 0xd8, 1 << 7); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 58 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 59 | /* Enable Backbone Clock Gating */ |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 60 | pci_or_config32(dev, 0xe1, (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 61 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 62 | /* Set VC0 transaction class */ |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 63 | pci_update_config32(dev, 0x114, ~0x000000ff, 1); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 64 | |
| 65 | /* Mask completion timeouts */ |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 66 | pci_or_config32(dev, 0x148, 1 << 14); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 67 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 68 | /* Enable common clock configuration */ |
| 69 | // Are there cases when we don't want that? |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 70 | pci_or_config16(dev, 0x50, 1 << 6); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 71 | |
Angel Pons | d19332c | 2020-06-08 12:32:54 +0200 | [diff] [blame^] | 72 | /* Clear errors in status registers. FIXME: Do something? */ |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 73 | reg16 = pci_read_config16(dev, 0x06); |
| 74 | //reg16 |= 0xf900; |
| 75 | pci_write_config16(dev, 0x06, reg16); |
| 76 | |
| 77 | reg16 = pci_read_config16(dev, 0x1e); |
| 78 | //reg16 |= 0xf900; |
| 79 | pci_write_config16(dev, 0x1e, reg16); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 80 | } |
| 81 | |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 82 | static int get_num_ports(void) |
| 83 | { |
| 84 | struct device *dev = pcidev_on_root(31, 0); |
| 85 | if (pci_read_config32(dev, FDVCT) & PCIE_4_PORTS_MAX) |
| 86 | return 4; |
| 87 | else |
| 88 | return 6; |
| 89 | } |
| 90 | |
| 91 | static void root_port_init_config(struct device *dev) |
| 92 | { |
| 93 | int rp; |
| 94 | |
| 95 | if (root_port_is_first(dev)) { |
| 96 | rpc.orig_rpfn = RCBA32(RPFN); |
| 97 | rpc.new_rpfn = rpc.orig_rpfn; |
| 98 | rpc.num_ports = get_num_ports(); |
| 99 | } |
| 100 | |
| 101 | rp = root_port_number(dev); |
| 102 | if (rp > rpc.num_ports) { |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 103 | printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", rp, rpc.num_ports); |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 104 | return; |
| 105 | } |
| 106 | |
| 107 | /* Cache pci device. */ |
| 108 | rpc.ports[rp - 1] = dev; |
| 109 | } |
| 110 | |
| 111 | /* Update devicetree with new Root Port function number assignment */ |
| 112 | static void ich_pcie_device_set_func(int index, int pci_func) |
| 113 | { |
| 114 | struct device *dev; |
| 115 | unsigned int new_devfn; |
| 116 | |
| 117 | dev = rpc.ports[index]; |
| 118 | |
| 119 | /* Set the new PCI function field for this Root Port. */ |
| 120 | rpc.new_rpfn &= ~RPFN_FNMASK(index); |
| 121 | rpc.new_rpfn |= RPFN_FNSET(index, pci_func); |
| 122 | |
| 123 | /* Determine the new devfn for this port */ |
| 124 | new_devfn = PCI_DEVFN(ICH_PCIE_DEV_SLOT, pci_func); |
| 125 | |
| 126 | if (dev->path.pci.devfn != new_devfn) { |
| 127 | printk(BIOS_DEBUG, |
| 128 | "ICH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 129 | PCI_SLOT(dev->path.pci.devfn), |
| 130 | PCI_FUNC(dev->path.pci.devfn), |
| 131 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 132 | |
| 133 | dev->path.pci.devfn = new_devfn; |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | static void root_port_commit_config(struct device *dev) |
| 138 | { |
| 139 | int i; |
| 140 | int coalesce = 0; |
| 141 | |
| 142 | if (dev->chip_info != NULL) { |
Elyes HAOUAS | 8d9a6f1 | 2020-04-28 04:57:27 +0200 | [diff] [blame] | 143 | const struct southbridge_intel_i82801gx_config *config = dev->chip_info; |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 144 | coalesce = config->pcie_port_coalesce; |
| 145 | } |
| 146 | |
| 147 | if (!rpc.ports[0]->enabled) |
| 148 | coalesce = 1; |
| 149 | |
| 150 | for (i = 0; i < rpc.num_ports; i++) { |
| 151 | struct device *pcie_dev; |
| 152 | |
| 153 | pcie_dev = rpc.ports[i]; |
| 154 | |
Jacob Garber | 14e826f | 2019-03-12 22:27:52 -0600 | [diff] [blame] | 155 | if (pcie_dev == NULL) { |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 156 | printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1); |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 157 | continue; |
| 158 | } |
| 159 | |
| 160 | if (pcie_dev->enabled) |
| 161 | continue; |
| 162 | |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 163 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(pcie_dev)); |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 164 | |
| 165 | /* Disable this device if possible */ |
| 166 | i82801gx_enable(pcie_dev); |
| 167 | } |
| 168 | |
| 169 | if (coalesce) { |
| 170 | int current_func; |
| 171 | |
| 172 | /* For all Root Ports N enabled ports get assigned the lower |
| 173 | * PCI function number. The disabled ones get upper PCI |
| 174 | * function numbers. */ |
| 175 | current_func = 0; |
| 176 | for (i = 0; i < rpc.num_ports; i++) { |
| 177 | if (!rpc.ports[i]->enabled) |
| 178 | continue; |
| 179 | ich_pcie_device_set_func(i, current_func); |
| 180 | current_func++; |
| 181 | } |
| 182 | |
| 183 | /* Allocate the disabled devices' PCI function number. */ |
| 184 | for (i = 0; i < rpc.num_ports; i++) { |
| 185 | if (rpc.ports[i]->enabled) |
| 186 | continue; |
| 187 | ich_pcie_device_set_func(i, current_func); |
| 188 | current_func++; |
| 189 | } |
| 190 | } |
| 191 | |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 192 | printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 193 | RCBA32(RPFN) = rpc.new_rpfn; |
| 194 | } |
| 195 | |
| 196 | static void ich_pcie_enable(struct device *dev) |
| 197 | { |
| 198 | /* Add this device to the root port config structure. */ |
| 199 | root_port_init_config(dev); |
| 200 | |
| 201 | /* |
| 202 | * When processing the last PCIe root port we can now |
| 203 | * update the Root Port Function Number and Hide register. |
| 204 | */ |
| 205 | if (root_port_is_last(dev)) |
| 206 | root_port_commit_config(dev); |
| 207 | } |
| 208 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 209 | static struct device_operations device_ops = { |
| 210 | .read_resources = pci_bus_read_resources, |
| 211 | .set_resources = pci_dev_set_resources, |
| 212 | .enable_resources = pci_bus_enable_resources, |
| 213 | .init = pci_init, |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 214 | .enable = ich_pcie_enable, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 215 | .scan_bus = pci_scan_bridge, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 216 | .ops_pci = &pci_dev_ops_pci, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 217 | }; |
| 218 | |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 219 | static const unsigned short i82801gx_pcie_ids[] = { |
| 220 | 0x27d0, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ |
| 221 | 0x27d2, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ |
| 222 | 0x27d4, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ |
| 223 | 0x27d6, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ |
| 224 | 0x27e0, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ |
| 225 | 0x27e2, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ |
| 226 | 0 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 227 | }; |
| 228 | |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 229 | static const struct pci_driver i82801gx_pcie __pci_driver = { |
Arthur Heymans | 3f111b0 | 2017-03-09 12:02:52 +0100 | [diff] [blame] | 230 | .ops = &device_ops, |
| 231 | .vendor = PCI_VENDOR_ID_INTEL, |
| 232 | .devices = i82801gx_pcie_ids, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 233 | }; |