sb/intel/i82801gx: Improve code formatting
This mainly updates the formatting for the new 96 characters text width.
Change-Id: Ia75c3ca7136b0291b3ae82e6a281cc76b75965ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40127
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 7efaca9..4398ad5 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -129,8 +129,7 @@
rp = root_port_number(dev);
if (rp > rpc.num_ports) {
- printk(BIOS_ERR, "Found Root Port %d, expecting %d\n",
- rp, rpc.num_ports);
+ printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", rp, rpc.num_ports);
return;
}
@@ -170,8 +169,7 @@
int coalesce = 0;
if (dev->chip_info != NULL) {
- struct southbridge_intel_i82801gx_config *config
- = dev->chip_info;
+ struct southbridge_intel_i82801gx_config *config = dev->chip_info;
coalesce = config->pcie_port_coalesce;
}
@@ -184,16 +182,14 @@
pcie_dev = rpc.ports[i];
if (pcie_dev == NULL) {
- printk(BIOS_ERR, "Root Port %d device is NULL?\n",
- i + 1);
+ printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1);
continue;
}
if (pcie_dev->enabled)
continue;
- printk(BIOS_DEBUG, "%s: Disabling device\n",
- dev_path(pcie_dev));
+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(pcie_dev));
/* Disable this device if possible */
i82801gx_enable(pcie_dev);
@@ -222,8 +218,7 @@
}
}
- printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n",
- rpc.orig_rpfn, rpc.new_rpfn);
+ printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn);
RCBA32(RPFN) = rpc.new_rpfn;
}