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review.coreboot.org / coreboot / debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 / . / src / southbridge / intel / i82801gx / i82801gx_pcie.c
blob: 729c78447c5e5f57c4350e9e6c6763f1e473237e [file] [log] [blame]
Stefan Reinauerdebb11f2008-10-29 04:46:52 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <console/console.h>
22#include <device/device.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
25
26static void pci_init(struct device *dev)
27{
28 u16 reg16;
29 u32 reg32;
30
31 printk_debug("Initializing ICH7 PCIe bridge.\n");
32#if 0
33 // When the latency of the PCIe(!) bridge is set to 0x20
34 // all devices on the secondary bus of the PCI(!) bridge
35 // suddenly vanish. If you know why, please explain here.
36
37 /* Set latency timer to 32. */
38 pci_write_config16(dev, 0x1b, 0x20);
39#endif
40
41 /* disable parity error response */
42 reg16 = pci_read_config16(dev, 0x3e);
43 reg16 &= ~(1 << 0);
44 pci_write_config16(dev, 0x3e, reg16);
45
46 /* Clear errors in status registers */
47 reg16 = pci_read_config16(dev, 0x06);
48 reg16 |= 0xf900;
49 pci_write_config16(dev, 0x06, reg16);
50
51 reg16 = pci_read_config16(dev, 0x1e);
52 reg16 |= 0xf900;
53 pci_write_config16(dev, 0x1e, reg16);
54
55 reg32 = pci_read_config32(dev, 0x20);
56 printk_debug(" MBL = 0x%08x\n", reg32);
57 reg32 = pci_read_config32(dev, 0x24);
58 printk_debug(" PMBL = 0x%08x\n", reg32);
59 reg32 = pci_read_config32(dev, 0x28);
60 printk_debug(" PMBU32 = 0x%08x\n", reg32);
61 reg32 = pci_read_config32(dev, 0x2c);
62 printk_debug(" PMLU32 = 0x%08x\n", reg32);
63}
64
65static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
66{
67 u32 pci_id;
68
69 printk_debug("Setting PCIe bridge subsystem ID.\n");
70 pci_id = pci_read_config32(dev, 0);
71 pci_write_config32(dev, 0x94, pci_id );
72}
73
74static struct pci_operations pci_ops = {
75 .set_subsystem = set_subsystem,
76};
77
78static struct device_operations device_ops = {
79 .read_resources = pci_bus_read_resources,
80 .set_resources = pci_dev_set_resources,
81 .enable_resources = pci_bus_enable_resources,
82 .init = pci_init,
83 .scan_bus = pci_scan_bridge,
84 .ops_pci = &pci_ops,
85};
86
87static const struct pci_driver i82801gx_pcie_port1 __pci_driver = {
88 .ops = &device_ops,
89 .vendor = 0x8086,
90 .device = 0x27d0,
91};
92
93static const struct pci_driver i82801gx_pcie_port2 __pci_driver = {
94 .ops = &device_ops,
95 .vendor = 0x8086,
96 .device = 0x27d2,
97};
98
99static const struct pci_driver i82801gx_pcie_port3 __pci_driver = {
100 .ops = &device_ops,
101 .vendor = 0x8086,
102 .device = 0x27d4,
103};
104
105static const struct pci_driver i82801gx_pcie_port4 __pci_driver = {
106 .ops = &device_ops,
107 .vendor = 0x8086,
108 .device = 0x27d6,
109};
110
111static const struct pci_driver i82801gx_pcie_port5 __pci_driver = {
112 .ops = &device_ops,
113 .vendor = 0x8086,
114 .device = 0x27e0,
115};
116
117static const struct pci_driver i82801gx_pcie_port6 __pci_driver = {
118 .ops = &device_ops,
119 .vendor = 0x8086,
120 .device = 0x27e2,
121};
122
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126