printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
index b66a887..d69bc6d 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c
@@ -28,7 +28,7 @@
u16 reg16;
u32 reg32;
- printk_debug("Initializing ICH7 PCIe bridge.\n");
+ printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
/* Enable Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -77,13 +77,13 @@
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
- printk_spew(" MBL = 0x%08x\n", reg32);
+ printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x24);
- printk_spew(" PMBL = 0x%08x\n", reg32);
+ printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x28);
- printk_spew(" PMBU32 = 0x%08x\n", reg32);
+ printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x2c);
- printk_spew(" PMLU32 = 0x%08x\n", reg32);
+ printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
#endif
/* Clear errors in status registers */