Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 6 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/chip.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <delay.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 12 | #include <types.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 13 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 14 | #include "raminit_native.h" |
| 15 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 16 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 17 | #include "sandybridge.h" |
| 18 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 19 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 20 | |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 21 | /* Number of programmed IOSAV subsequences. */ |
| 22 | static unsigned int ssq_count = 0; |
| 23 | |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 24 | static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq) |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 25 | { |
| 26 | MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw; |
| 27 | MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw; |
| 28 | MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw; |
| 29 | MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw; |
| 30 | |
| 31 | ssq_count++; |
| 32 | } |
| 33 | |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 34 | static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 35 | { |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 36 | MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); |
| 37 | |
| 38 | ssq_count = 0; |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 39 | } |
Angel Pons | ad70400 | 2020-05-02 22:51:58 +0200 | [diff] [blame] | 40 | |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 41 | static void iosav_run_once(const int ch) |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 42 | { |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 43 | iosav_run_queue(ch, 1, 0); |
Angel Pons | e7afcd53 | 2020-05-02 23:14:27 +0200 | [diff] [blame] | 44 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 45 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 46 | static void sfence(void) |
| 47 | { |
| 48 | asm volatile ("sfence"); |
| 49 | } |
| 50 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 51 | /* Toggle IO reset bit */ |
| 52 | static void toggle_io_reset(void) |
| 53 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 54 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 55 | MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 56 | udelay(1); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 57 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 58 | udelay(1); |
| 59 | } |
| 60 | |
| 61 | static u32 get_XOVER_CLK(u8 rankmap) |
| 62 | { |
| 63 | return rankmap << 24; |
| 64 | } |
| 65 | |
| 66 | static u32 get_XOVER_CMD(u8 rankmap) |
| 67 | { |
| 68 | u32 reg; |
| 69 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 70 | /* Enable xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 71 | reg = 0x4000; |
| 72 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 73 | /* Enable xover ctl */ |
| 74 | if (rankmap & 0x03) |
| 75 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 76 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 77 | if (rankmap & 0x0c) |
| 78 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 79 | |
| 80 | return reg; |
| 81 | } |
| 82 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 83 | /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 84 | u8 get_CWL(u32 tCK) |
| 85 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 86 | /* Get CWL based on tCK using the following rule */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 87 | switch (tCK) { |
| 88 | case TCK_1333MHZ: |
| 89 | return 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 90 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 91 | case TCK_1200MHZ: |
| 92 | case TCK_1100MHZ: |
| 93 | return 11; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 94 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 95 | case TCK_1066MHZ: |
| 96 | case TCK_1000MHZ: |
| 97 | return 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 98 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 99 | case TCK_933MHZ: |
| 100 | case TCK_900MHZ: |
| 101 | return 9; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 102 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 103 | case TCK_800MHZ: |
| 104 | case TCK_700MHZ: |
| 105 | return 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 106 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 107 | case TCK_666MHZ: |
| 108 | return 7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 109 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 110 | case TCK_533MHZ: |
| 111 | return 6; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 112 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 113 | default: |
| 114 | return 5; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | void dram_find_common_params(ramctr_timing *ctrl) |
| 119 | { |
| 120 | size_t valid_dimms; |
| 121 | int channel, slot; |
| 122 | dimm_info *dimms = &ctrl->info; |
| 123 | |
| 124 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 125 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 126 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 127 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 128 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 129 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 130 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 131 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 132 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 133 | valid_dimms++; |
| 134 | |
| 135 | /* Find all possible CAS combinations */ |
| 136 | ctrl->cas_supported &= dimm->cas_supported; |
| 137 | |
| 138 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 139 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 140 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 141 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 142 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 143 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 144 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 145 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 146 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 147 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 148 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 149 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 150 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 151 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 155 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 156 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 157 | if (!valid_dimms) |
| 158 | die("No valid DIMMs found"); |
| 159 | } |
| 160 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 161 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 162 | { |
| 163 | u32 reg; |
| 164 | int channel; |
| 165 | |
| 166 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 167 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 168 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 169 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 170 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 171 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 172 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 173 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 174 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 175 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 179 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 180 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 181 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 182 | |
| 183 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 184 | /* |
| 185 | * ODT stretch: |
| 186 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 187 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 188 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 189 | if (stretch == 2) |
| 190 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 191 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 192 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 193 | MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); |
| 194 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 195 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 196 | addr = TC_OTHP_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 197 | MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 198 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 199 | } |
| 200 | } |
| 201 | |
| 202 | void dram_timing_regs(ramctr_timing *ctrl) |
| 203 | { |
| 204 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 205 | int channel; |
| 206 | |
| 207 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 208 | /* BIN parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 209 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 210 | reg |= (ctrl->tRCD << 0); |
| 211 | reg |= (ctrl->tRP << 4); |
| 212 | reg |= (ctrl->CAS << 8); |
| 213 | reg |= (ctrl->CWL << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 214 | reg |= (ctrl->tRAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 215 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); |
| 216 | MCHBAR32(TC_DBP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 217 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 218 | /* Regular access parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 219 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 220 | reg |= (ctrl->tRRD << 0); |
| 221 | reg |= (ctrl->tRTP << 4); |
| 222 | reg |= (ctrl->tCKE << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 223 | reg |= (ctrl->tWTR << 12); |
| 224 | reg |= (ctrl->tFAW << 16); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 225 | reg |= (ctrl->tWR << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 226 | reg |= (3 << 30); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 227 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); |
| 228 | MCHBAR32(TC_RAP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 229 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 230 | /* Other parameters */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 231 | addr = TC_OTHP_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 232 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | reg |= (ctrl->tXPDLL << 0); |
| 234 | reg |= (ctrl->tXP << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 235 | reg |= (ctrl->tAONPD << 8); |
| 236 | reg |= 0xa0000; |
| 237 | printram("OTHP [%x] = %x\n", addr, reg); |
| 238 | MCHBAR32(addr) = reg; |
| 239 | |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 240 | /* Debug parameters - only applies to Ivy Bridge */ |
| 241 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 242 | reg = 0; |
| 243 | |
| 244 | /* |
| 245 | * If tXP and tXPDLL are very high, we need to increase them by one. |
| 246 | * This can only happen on Ivy Bridge, and when overclocking the RAM. |
| 247 | */ |
| 248 | if (ctrl->tXP >= 8) |
| 249 | reg |= (1 << 12); |
| 250 | |
| 251 | if (ctrl->tXPDLL >= 32) |
| 252 | reg |= (1 << 13); |
| 253 | |
| 254 | MCHBAR32(TC_DTP_ch(channel)) = reg; |
| 255 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 256 | |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 257 | MCHBAR32_OR(addr, 0x00020000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 258 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 259 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 260 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 261 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 262 | * TC-Refresh timing parameters: |
| 263 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 264 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 265 | */ |
| 266 | val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 267 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 268 | reg = ((ctrl->tREFI & 0xffff) << 0) | |
| 269 | ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); |
| 270 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 271 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); |
| 272 | MCHBAR32(TC_RFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 273 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 274 | MCHBAR32_OR(TC_RFP_ch(channel), 0xff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 275 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 276 | /* Self-refresh timing parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 277 | reg = 0; |
| 278 | val32 = tDLLK; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 279 | reg = (reg & ~0x00000fff) | (val32 << 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 280 | val32 = ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 281 | reg = (reg & ~0x0000f000) | (val32 << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 282 | val32 = tDLLK - ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 283 | reg = (reg & ~0x03ff0000) | (val32 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 284 | val32 = ctrl->tMOD - 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 285 | reg = (reg & ~0xf0000000) | (val32 << 28); |
| 286 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 287 | MCHBAR32(TC_SRFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 288 | } |
| 289 | } |
| 290 | |
| 291 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 292 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 293 | int channel; |
| 294 | dimm_info *info = &ctrl->info; |
| 295 | |
| 296 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 297 | dimm_attr *dimmA, *dimmB; |
| 298 | u32 reg = 0; |
| 299 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 300 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 301 | dimmA = &info->dimm[channel][0]; |
| 302 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 303 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 304 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 305 | dimmA = &info->dimm[channel][1]; |
| 306 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 307 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 308 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 309 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 310 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 311 | reg |= (dimmA->size_mb / 256) << 0; |
| 312 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 313 | reg |= (dimmA->width / 8 - 1) << 19; |
| 314 | } |
| 315 | |
| 316 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 317 | reg |= (dimmB->size_mb / 256) << 8; |
| 318 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 319 | reg |= (dimmB->width / 8 - 1) << 20; |
| 320 | } |
| 321 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 322 | reg |= 1 << 21; /* Rank interleave */ |
| 323 | reg |= 1 << 22; /* Enhanced interleave */ |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 324 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 325 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 326 | ctrl->mad_dimm[channel] = reg; |
| 327 | } else { |
| 328 | ctrl->mad_dimm[channel] = 0; |
| 329 | } |
| 330 | } |
| 331 | } |
| 332 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 333 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 334 | { |
| 335 | int channel; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 336 | u32 ecc; |
| 337 | |
| 338 | if (ctrl->ecc_enabled) |
| 339 | ecc = training ? (1 << 24) : (3 << 24); |
| 340 | else |
| 341 | ecc = 0; |
| 342 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 343 | FOR_ALL_CHANNELS { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 344 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 345 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 346 | |
| 347 | //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 348 | } |
| 349 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 350 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 351 | { |
| 352 | u32 reg, ch0size, ch1size; |
| 353 | u8 val; |
| 354 | reg = 0; |
| 355 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 356 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 357 | if (training) { |
| 358 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 359 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 360 | } else { |
| 361 | ch0size = ctrl->channel_size_mb[0]; |
| 362 | ch1size = ctrl->channel_size_mb[1]; |
| 363 | } |
| 364 | |
| 365 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 366 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 367 | val = ch1size / 256; |
| 368 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 369 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 370 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 371 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 372 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 373 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 374 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 375 | val = ch0size / 256; |
| 376 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 377 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 378 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 379 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 380 | } |
| 381 | } |
| 382 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 383 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 384 | |
| 385 | static unsigned int get_mmio_size(void) |
| 386 | { |
| 387 | const struct device *dev; |
| 388 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 389 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 390 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 391 | if (dev) |
| 392 | cfg = dev->chip_info; |
| 393 | |
| 394 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 395 | if (!cfg || cfg->pci_mmio_size == 0) |
| 396 | return DEFAULT_PCI_MMIO_SIZE; |
| 397 | else |
| 398 | return cfg->pci_mmio_size; |
| 399 | } |
| 400 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 401 | /* |
| 402 | * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. |
| 403 | * The ME/PCU/.. has the ability to change this. |
| 404 | * Return 0: ECC is optional |
| 405 | * Return 1: ECC is forced |
| 406 | */ |
| 407 | bool get_host_ecc_forced(void) |
| 408 | { |
| 409 | /* read Capabilities A Register */ |
| 410 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 411 | return !!(reg32 & (1 << 24)); |
| 412 | } |
| 413 | |
| 414 | /* |
| 415 | * Returns the ECC capability. |
| 416 | * The ME/PCU/.. has the ability to change this. |
| 417 | * Return 0: ECC is disabled |
| 418 | * Return 1: ECC is possible |
| 419 | */ |
| 420 | bool get_host_ecc_cap(void) |
| 421 | { |
| 422 | /* read Capabilities A Register */ |
| 423 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 424 | return !(reg32 & (1 << 25)); |
| 425 | } |
| 426 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 427 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 428 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 429 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 430 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 431 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 432 | uint16_t ggc; |
| 433 | |
| 434 | mmiosize = get_mmio_size(); |
| 435 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 436 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 437 | if (!(ggc & 2)) { |
| 438 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 439 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 440 | } else { |
| 441 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 442 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 446 | |
| 447 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 448 | |
| 449 | mestolenbase = tom - me_uma_size; |
| 450 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 451 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 452 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 453 | gfxstolenbase = toludbase - gfxstolen; |
| 454 | gttbase = gfxstolenbase - gttsize; |
| 455 | |
| 456 | tsegbase = gttbase - tsegsize; |
| 457 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 458 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 459 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 460 | tsegbase &= ~(tsegsize - 1); |
| 461 | |
| 462 | gttbase -= tsegbasedelta; |
| 463 | gfxstolenbase -= tsegbasedelta; |
| 464 | toludbase -= tsegbasedelta; |
| 465 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 466 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 467 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 468 | /* Reclaim is possible */ |
| 469 | reclaim = 1; |
| 470 | remapbase = MAX(4096, tom - me_uma_size); |
| 471 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 472 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 473 | } else { |
| 474 | // Reclaim not possible |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 475 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 476 | touudbase = tom - me_uma_size; |
| 477 | } |
| 478 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 479 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 480 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 481 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 482 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 483 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 484 | val = tom & 0xfff; |
| 485 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 486 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 487 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 488 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 489 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 490 | val = tom & 0xfffff000; |
| 491 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 492 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 493 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 494 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 495 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 496 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 497 | val = toludbase & 0xfff; |
| 498 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 499 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 500 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 501 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 502 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 503 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 504 | val = touudbase & 0xfff; |
| 505 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 506 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 507 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 508 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 509 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 510 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 511 | val = touudbase & 0xfffff000; |
| 512 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 513 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 514 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 515 | |
| 516 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 517 | /* REMAP BASE */ |
| 518 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 519 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 520 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 521 | /* REMAP LIMIT */ |
| 522 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 523 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 524 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 525 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 526 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 527 | val = tsegbase & 0xfff; |
| 528 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 529 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 530 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 531 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 532 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 533 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 534 | val = gfxstolenbase & 0xfff; |
| 535 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 536 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 537 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 538 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 539 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 540 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 541 | val = gttbase & 0xfff; |
| 542 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 543 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 544 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 545 | |
| 546 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 547 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 548 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 549 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 550 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 551 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 552 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 553 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 554 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 555 | val = mestolenbase & 0xfff; |
| 556 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 557 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 558 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 559 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 560 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 561 | val = mestolenbase & 0xfffff000; |
| 562 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 563 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 564 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 565 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 567 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 568 | val = (0x80000 - me_uma_size) & 0xfff; |
| 569 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 570 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 571 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 572 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 573 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 574 | } |
| 575 | } |
| 576 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 577 | static void wait_for_iosav(int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 578 | { |
| 579 | while (1) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 580 | if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 581 | return; |
| 582 | } |
| 583 | } |
| 584 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 585 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 586 | { |
| 587 | int channel, slotrank; |
| 588 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 589 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 590 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 591 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 592 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 593 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 594 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 595 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 596 | |
| 597 | /* DRAM command ZQCS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 598 | { |
| 599 | const struct iosav_ssq ssq = { |
| 600 | .sp_cmd_ctrl = { |
| 601 | .command = IOSAV_ZQCS, |
| 602 | }, |
| 603 | .subseq_ctrl = { |
| 604 | .cmd_executions = 1, |
| 605 | .cmd_delay_gap = 3, |
| 606 | .post_ssq_wait = 8, |
| 607 | .data_direction = SSQ_NA, |
| 608 | }, |
| 609 | .sp_cmd_addr = { |
| 610 | .address = 0, |
| 611 | .rowbits = 6, |
| 612 | .bank = 0, |
| 613 | .rank = slotrank, |
| 614 | }, |
| 615 | }; |
| 616 | iosav_write_ssq(channel, &ssq); |
| 617 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 618 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 619 | /* |
| 620 | * Execute command queue - why is bit 22 set here?! |
| 621 | * |
| 622 | * This is actually using the IOSAV state machine as a timer, so refresh is allowed. |
| 623 | */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 624 | iosav_run_queue(channel, 1, 1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 625 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 626 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 627 | } |
| 628 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 629 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 630 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 631 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 632 | int channel; |
| 633 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 634 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 635 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 636 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 637 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 638 | } while ((reg & 0x14) == 0); |
| 639 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 640 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 641 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 642 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 643 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 644 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 645 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 646 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 647 | /* Assert DIMM reset signal */ |
| 648 | MCHBAR32_AND(MC_INIT_STATE_G, ~2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 649 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 650 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 651 | udelay(200); |
| 652 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 653 | /* Deassert DIMM reset signal */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 654 | MCHBAR32_OR(MC_INIT_STATE_G, 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 655 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 656 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 657 | udelay(500); |
| 658 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 659 | /* Enable DCLK */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 660 | MCHBAR32_OR(MC_INIT_STATE_G, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 661 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 662 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 663 | udelay(1); |
| 664 | |
| 665 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 666 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 667 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 668 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 669 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 670 | /* Wait 10ns for ranks to settle */ |
| 671 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 672 | |
| 673 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 674 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 675 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 676 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 677 | write_reset(ctrl); |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) |
| 682 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 683 | /* Get ODT based on rankmap */ |
| 684 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 685 | |
| 686 | if (dimms_per_ch == 1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 687 | return (const odtmap){60, 60}; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 688 | } else { |
| 689 | return (const odtmap){120, 30}; |
| 690 | } |
| 691 | } |
| 692 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 693 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 694 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 695 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 696 | |
| 697 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 698 | /* DDR3 Rank1 Address mirror |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 699 | swap the following pins: |
| 700 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 701 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 702 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 703 | } |
| 704 | |
| 705 | /* DRAM command MRS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 706 | { |
| 707 | const struct iosav_ssq ssq = { |
| 708 | .sp_cmd_ctrl = { |
| 709 | .command = IOSAV_MRS, |
| 710 | }, |
| 711 | .subseq_ctrl = { |
| 712 | .cmd_executions = 1, |
| 713 | .cmd_delay_gap = 4, |
| 714 | .post_ssq_wait = 4, |
| 715 | .data_direction = SSQ_NA, |
| 716 | }, |
| 717 | .sp_cmd_addr = { |
| 718 | .address = val, |
| 719 | .rowbits = 6, |
| 720 | .bank = reg, |
| 721 | .rank = slotrank, |
| 722 | }, |
| 723 | }; |
| 724 | iosav_write_ssq(channel, &ssq); |
| 725 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 726 | |
| 727 | /* DRAM command MRS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 728 | { |
| 729 | const struct iosav_ssq ssq = { |
| 730 | .sp_cmd_ctrl = { |
| 731 | .command = IOSAV_MRS, |
| 732 | .ranksel_ap = 1, |
| 733 | }, |
| 734 | .subseq_ctrl = { |
| 735 | .cmd_executions = 1, |
| 736 | .cmd_delay_gap = 4, |
| 737 | .post_ssq_wait = 4, |
| 738 | .data_direction = SSQ_NA, |
| 739 | }, |
| 740 | .sp_cmd_addr = { |
| 741 | .address = val, |
| 742 | .rowbits = 6, |
| 743 | .bank = reg, |
| 744 | .rank = slotrank, |
| 745 | }, |
| 746 | }; |
| 747 | iosav_write_ssq(channel, &ssq); |
| 748 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 749 | |
| 750 | /* DRAM command MRS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 751 | { |
| 752 | const struct iosav_ssq ssq = { |
| 753 | .sp_cmd_ctrl = { |
| 754 | .command = IOSAV_MRS, |
| 755 | }, |
| 756 | .subseq_ctrl = { |
| 757 | .cmd_executions = 1, |
| 758 | .cmd_delay_gap = 4, |
| 759 | .post_ssq_wait = ctrl->tMOD, |
| 760 | .data_direction = SSQ_NA, |
| 761 | }, |
| 762 | .sp_cmd_addr = { |
| 763 | .address = val, |
| 764 | .rowbits = 6, |
| 765 | .bank = reg, |
| 766 | .rank = slotrank, |
| 767 | }, |
| 768 | }; |
| 769 | iosav_write_ssq(channel, &ssq); |
| 770 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 771 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 772 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 773 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 774 | } |
| 775 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 776 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 777 | { |
| 778 | u16 mr0reg, mch_cas, mch_wr; |
| 779 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 780 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 781 | |
| 782 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 783 | mr0reg = 0x100; |
| 784 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 785 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 786 | if (ctrl->CAS < 12) { |
| 787 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 788 | } else { |
| 789 | mch_cas = (u16) (ctrl->CAS - 12); |
| 790 | mch_cas = ((mch_cas << 1) | 0x1); |
| 791 | } |
| 792 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 793 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 794 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 795 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 796 | mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); |
| 797 | mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); |
| 798 | mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 799 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 800 | /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ |
| 801 | mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 802 | return mr0reg; |
| 803 | } |
| 804 | |
| 805 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 806 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 807 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 808 | } |
| 809 | |
| 810 | static u32 encode_odt(u32 odt) |
| 811 | { |
| 812 | switch (odt) { |
| 813 | case 30: |
| 814 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 815 | case 60: |
| 816 | return (1 << 2); // RZQ/4 |
| 817 | case 120: |
| 818 | return (1 << 6); // RZQ/2 |
| 819 | default: |
| 820 | case 0: |
| 821 | return 0; |
| 822 | } |
| 823 | } |
| 824 | |
| 825 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 826 | { |
| 827 | odtmap odt; |
| 828 | u32 mr1reg; |
| 829 | |
| 830 | odt = get_ODT(ctrl, rank, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 831 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 832 | |
| 833 | mr1reg |= encode_odt(odt.rttnom); |
| 834 | |
| 835 | return mr1reg; |
| 836 | } |
| 837 | |
| 838 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 839 | { |
| 840 | u16 mr1reg; |
| 841 | |
| 842 | mr1reg = make_mr1(ctrl, rank, channel); |
| 843 | |
| 844 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 845 | } |
| 846 | |
| 847 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 848 | { |
| 849 | u16 pasr, cwl, mr2reg; |
| 850 | odtmap odt; |
| 851 | int srt; |
| 852 | |
| 853 | pasr = 0; |
| 854 | cwl = ctrl->CWL - 5; |
| 855 | odt = get_ODT(ctrl, rank, channel); |
| 856 | |
| 857 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
| 858 | |
| 859 | mr2reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 860 | mr2reg = (mr2reg & ~0x07) | pasr; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 861 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 862 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 863 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 864 | mr2reg |= (odt.rttwr / 60) << 9; |
| 865 | |
| 866 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
| 867 | } |
| 868 | |
| 869 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 870 | { |
| 871 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 872 | } |
| 873 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 874 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 875 | { |
| 876 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 877 | int channel; |
| 878 | |
| 879 | FOR_ALL_POPULATED_CHANNELS { |
| 880 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 881 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 882 | dram_mr2(ctrl, slotrank, channel); |
| 883 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 884 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 885 | dram_mr3(ctrl, slotrank, channel); |
| 886 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 887 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 888 | dram_mr1(ctrl, slotrank, channel); |
| 889 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 890 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 891 | dram_mr0(ctrl, slotrank, channel); |
| 892 | } |
| 893 | } |
| 894 | |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 895 | /* DRAM command NOP (without ODT nor chip selects) */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 896 | { |
| 897 | const struct iosav_ssq ssq = { |
| 898 | .sp_cmd_ctrl = { |
| 899 | .command = IOSAV_NOP & ~(0xff << 8), |
| 900 | }, |
| 901 | .subseq_ctrl = { |
| 902 | .cmd_executions = 1, |
| 903 | .cmd_delay_gap = 4, |
| 904 | .post_ssq_wait = 15, |
| 905 | .data_direction = SSQ_NA, |
| 906 | }, |
| 907 | .sp_cmd_addr = { |
| 908 | .address = 2, |
| 909 | .rowbits = 6, |
| 910 | .bank = 0, |
| 911 | .rank = 0, |
| 912 | }, |
| 913 | }; |
| 914 | iosav_write_ssq(BROADCAST_CH, &ssq); |
| 915 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 916 | |
| 917 | /* DRAM command ZQCL */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 918 | { |
| 919 | const struct iosav_ssq ssq = { |
| 920 | .sp_cmd_ctrl = { |
| 921 | .command = IOSAV_ZQCS, |
| 922 | .ranksel_ap = 1, |
| 923 | }, |
| 924 | .subseq_ctrl = { |
| 925 | .cmd_executions = 1, |
| 926 | .cmd_delay_gap = 4, |
| 927 | .post_ssq_wait = 400, |
| 928 | .data_direction = SSQ_NA, |
| 929 | }, |
| 930 | .sp_cmd_addr = { |
| 931 | .address = 1024, |
| 932 | .rowbits = 6, |
| 933 | .bank = 0, |
| 934 | .rank = 0, |
| 935 | }, |
| 936 | .addr_update = { |
| 937 | .inc_rank = 1, |
| 938 | .addr_wrap = 20, |
| 939 | }, |
| 940 | }; |
| 941 | iosav_write_ssq(BROADCAST_CH, &ssq); |
| 942 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 943 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 944 | /* Execute command queue on all channels. Do it four times. */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 945 | iosav_run_queue(BROADCAST_CH, 4, 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 946 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 947 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 948 | /* Wait for ref drained */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 949 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 950 | } |
| 951 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 952 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 953 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 954 | |
| 955 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 956 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 957 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 958 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 959 | |
| 960 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 961 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 962 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 963 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 964 | |
| 965 | /* DRAM command ZQCS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 966 | { |
| 967 | const struct iosav_ssq ssq = { |
| 968 | .sp_cmd_ctrl = { |
| 969 | .command = IOSAV_ZQCS, |
| 970 | }, |
| 971 | .subseq_ctrl = { |
| 972 | .cmd_executions = 1, |
| 973 | .cmd_delay_gap = 4, |
| 974 | .post_ssq_wait = 101, |
| 975 | .data_direction = SSQ_NA, |
| 976 | }, |
| 977 | .sp_cmd_addr = { |
| 978 | .address = 0, |
| 979 | .rowbits = 6, |
| 980 | .bank = 0, |
| 981 | .rank = slotrank, |
| 982 | }, |
| 983 | .addr_update = { |
| 984 | .addr_wrap = 31, |
| 985 | }, |
| 986 | }; |
| 987 | iosav_write_ssq(channel, &ssq); |
| 988 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 989 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 990 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 991 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 992 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 993 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 994 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 995 | } |
| 996 | } |
| 997 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 998 | static const u32 lane_base[] = { |
| 999 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 1000 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 1001 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1002 | }; |
| 1003 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1004 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1005 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1006 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1007 | int lane; |
| 1008 | int slotrank, slot; |
| 1009 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1010 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1011 | |
| 1012 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1013 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 1014 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1015 | } |
| 1016 | |
| 1017 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 1018 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 1019 | case 0: |
| 1020 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1021 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1022 | break; |
| 1023 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1024 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1025 | ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1026 | break; |
| 1027 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1028 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1029 | ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1030 | break; |
| 1031 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1032 | pi_coding_ctrl[slot] = |
| 1033 | (ctrl->timings[channel][2 * slot].pi_coding + |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1034 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1035 | break; |
| 1036 | } |
| 1037 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1038 | /* Enable CMD XOVER */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1039 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1040 | reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; |
| 1041 | reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1042 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1043 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 1044 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1045 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1046 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1047 | /* Enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1048 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 1049 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1050 | |
| 1051 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1052 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1053 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1054 | if (shift < 0) |
| 1055 | shift = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1056 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1057 | offset_pi_code = ctrl->pi_code_offset + shift; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1058 | |
| 1059 | /* Set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1060 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 1061 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1062 | } |
| 1063 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1064 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 1065 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1066 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1067 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 1068 | reg_io_latency &= 0xffff0000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1069 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1070 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1071 | |
| 1072 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1073 | int post_timA_min_high = 7, pre_timA_min_high = 7; |
| 1074 | int post_timA_max_high = 0, pre_timA_max_high = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1075 | int shift_402x = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1076 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1077 | |
| 1078 | if (shift < 0) |
| 1079 | shift = 0; |
| 1080 | |
| 1081 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 1082 | post_timA_min_high = MIN(post_timA_min_high, |
| 1083 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1084 | timA + shift) >> 6); |
| 1085 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 1086 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1087 | timA >> 6); |
| 1088 | post_timA_max_high = MAX(post_timA_max_high, |
| 1089 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 1090 | timA + shift) >> 6); |
| 1091 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 1092 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 1093 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1094 | } |
| 1095 | |
| 1096 | if (pre_timA_max_high - pre_timA_min_high < |
| 1097 | post_timA_max_high - post_timA_min_high) |
| 1098 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1099 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1100 | else if (pre_timA_max_high - pre_timA_min_high > |
| 1101 | post_timA_max_high - post_timA_min_high) |
| 1102 | shift_402x = -1; |
| 1103 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 1104 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1105 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1106 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1107 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1108 | reg_roundtrip_latency |= |
| 1109 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1110 | shift_402x) << (8 * slotrank); |
| 1111 | |
| 1112 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1113 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1114 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1115 | timA + shift) & 0x3f) |
| 1116 | | |
| 1117 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1118 | rising + shift) << 8) |
| 1119 | | |
| 1120 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1121 | timA + shift - |
| 1122 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 1123 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1124 | falling + shift) << 20)); |
| 1125 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1126 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1127 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1128 | timC + shift) & 0x3f) |
| 1129 | | |
| 1130 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1131 | timB + shift) & 0x3f) << 8) |
| 1132 | | |
| 1133 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1134 | timB + shift) & 0x1c0) << 9) |
| 1135 | | |
| 1136 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1137 | timC + shift) & 0x40) << 13)); |
| 1138 | } |
| 1139 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1140 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1141 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1142 | } |
| 1143 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1144 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1145 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1146 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1147 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1148 | /* |
| 1149 | * DRAM command MRS |
| 1150 | * |
| 1151 | * Write MR3 MPR enable. |
| 1152 | * In this mode only RD and RDA are allowed, and all reads return a predefined pattern. |
| 1153 | */ |
| 1154 | { |
| 1155 | const struct iosav_ssq ssq = { |
| 1156 | .sp_cmd_ctrl = { |
| 1157 | .command = IOSAV_MRS, |
| 1158 | .ranksel_ap = 1, |
| 1159 | }, |
| 1160 | .subseq_ctrl = { |
| 1161 | .cmd_executions = 1, |
| 1162 | .cmd_delay_gap = 3, |
| 1163 | .post_ssq_wait = ctrl->tMOD, |
| 1164 | .data_direction = SSQ_NA, |
| 1165 | }, |
| 1166 | .sp_cmd_addr = { |
| 1167 | .address = 4, |
| 1168 | .rowbits = 6, |
| 1169 | .bank = 3, |
| 1170 | .rank = slotrank, |
| 1171 | }, |
| 1172 | }; |
| 1173 | iosav_write_ssq(channel, &ssq); |
| 1174 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1175 | |
| 1176 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1177 | { |
| 1178 | const struct iosav_ssq ssq = { |
| 1179 | .sp_cmd_ctrl = { |
| 1180 | .command = IOSAV_RD, |
| 1181 | .ranksel_ap = 1, |
| 1182 | }, |
| 1183 | .subseq_ctrl = { |
| 1184 | .cmd_executions = 1, |
| 1185 | .cmd_delay_gap = 3, |
| 1186 | .post_ssq_wait = 4, |
| 1187 | .data_direction = SSQ_RD, |
| 1188 | }, |
| 1189 | .sp_cmd_addr = { |
| 1190 | .address = 0, |
| 1191 | .rowbits = 0, |
| 1192 | .bank = 0, |
| 1193 | .rank = slotrank, |
| 1194 | }, |
| 1195 | }; |
| 1196 | iosav_write_ssq(channel, &ssq); |
| 1197 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1198 | |
| 1199 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1200 | { |
| 1201 | const struct iosav_ssq ssq = { |
| 1202 | .sp_cmd_ctrl = { |
| 1203 | .command = IOSAV_RD, |
| 1204 | .ranksel_ap = 1, |
| 1205 | }, |
| 1206 | .subseq_ctrl = { |
| 1207 | .cmd_executions = 15, |
| 1208 | .cmd_delay_gap = 4, |
| 1209 | .post_ssq_wait = ctrl->CAS + 36, |
| 1210 | .data_direction = SSQ_NA, |
| 1211 | }, |
| 1212 | .sp_cmd_addr = { |
| 1213 | .address = 0, |
| 1214 | .rowbits = 6, |
| 1215 | .bank = 0, |
| 1216 | .rank = slotrank, |
| 1217 | }, |
| 1218 | }; |
| 1219 | iosav_write_ssq(channel, &ssq); |
| 1220 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1221 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1222 | /* |
| 1223 | * DRAM command MRS |
| 1224 | * |
| 1225 | * Write MR3 MPR disable. |
| 1226 | */ |
| 1227 | { |
| 1228 | const struct iosav_ssq ssq = { |
| 1229 | .sp_cmd_ctrl = { |
| 1230 | .command = IOSAV_MRS, |
| 1231 | .ranksel_ap = 1, |
| 1232 | }, |
| 1233 | .subseq_ctrl = { |
| 1234 | .cmd_executions = 1, |
| 1235 | .cmd_delay_gap = 3, |
| 1236 | .post_ssq_wait = ctrl->tMOD, |
| 1237 | .data_direction = SSQ_NA, |
| 1238 | }, |
| 1239 | .sp_cmd_addr = { |
| 1240 | .address = 0, |
| 1241 | .rowbits = 6, |
| 1242 | .bank = 3, |
| 1243 | .rank = slotrank, |
| 1244 | }, |
| 1245 | }; |
| 1246 | iosav_write_ssq(channel, &ssq); |
| 1247 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1248 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1249 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1250 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1251 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1252 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1253 | } |
| 1254 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1255 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1256 | { |
| 1257 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1258 | |
| 1259 | return (MCHBAR32(lane_base[lane] + |
| 1260 | GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1261 | } |
| 1262 | |
| 1263 | struct run { |
| 1264 | int middle; |
| 1265 | int end; |
| 1266 | int start; |
| 1267 | int all; |
| 1268 | int length; |
| 1269 | }; |
| 1270 | |
| 1271 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1272 | { |
| 1273 | int i, ls; |
| 1274 | int bl = 0, bs = 0; |
| 1275 | struct run ret; |
| 1276 | |
| 1277 | ls = 0; |
| 1278 | for (i = 0; i < 2 * sz; i++) |
| 1279 | if (seq[i % sz]) { |
| 1280 | if (i - ls > bl) { |
| 1281 | bl = i - ls; |
| 1282 | bs = ls; |
| 1283 | } |
| 1284 | ls = i + 1; |
| 1285 | } |
| 1286 | if (bl == 0) { |
| 1287 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1288 | ret.start = 0; |
| 1289 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1290 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1291 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1292 | return ret; |
| 1293 | } |
| 1294 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1295 | ret.start = bs % sz; |
| 1296 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1297 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1298 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1299 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1300 | |
| 1301 | return ret; |
| 1302 | } |
| 1303 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1304 | static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1305 | { |
| 1306 | int timA; |
| 1307 | int statistics[NUM_LANES][128]; |
| 1308 | int lane; |
| 1309 | |
| 1310 | for (timA = 0; timA < 128; timA++) { |
| 1311 | FOR_ALL_LANES { |
| 1312 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1313 | } |
| 1314 | program_timings(ctrl, channel); |
| 1315 | |
| 1316 | test_timA(ctrl, channel, slotrank); |
| 1317 | |
| 1318 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1319 | statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1320 | } |
| 1321 | } |
| 1322 | FOR_ALL_LANES { |
| 1323 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1324 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1325 | upperA[lane] = rn.end; |
| 1326 | if (upperA[lane] < rn.middle) |
| 1327 | upperA[lane] += 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1328 | |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1329 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1330 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1331 | } |
| 1332 | } |
| 1333 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1334 | static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1335 | { |
| 1336 | int timA_delta; |
| 1337 | int statistics[NUM_LANES][51]; |
| 1338 | int lane, i; |
| 1339 | |
| 1340 | memset(statistics, 0, sizeof(statistics)); |
| 1341 | |
| 1342 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1343 | |
| 1344 | FOR_ALL_LANES { |
| 1345 | ctrl->timings[channel][slotrank].lanes[lane].timA |
| 1346 | = upperA[lane] + timA_delta + 0x40; |
| 1347 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1348 | program_timings(ctrl, channel); |
| 1349 | |
| 1350 | for (i = 0; i < 100; i++) { |
| 1351 | test_timA(ctrl, channel, slotrank); |
| 1352 | FOR_ALL_LANES { |
| 1353 | statistics[lane][timA_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1354 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1355 | } |
| 1356 | } |
| 1357 | } |
| 1358 | FOR_ALL_LANES { |
| 1359 | int last_zero, first_all; |
| 1360 | |
| 1361 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1362 | if (statistics[lane][last_zero + 25]) |
| 1363 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1364 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1365 | last_zero--; |
| 1366 | for (first_all = -25; first_all <= 25; first_all++) |
| 1367 | if (statistics[lane][first_all + 25] == 100) |
| 1368 | break; |
| 1369 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1370 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1371 | |
| 1372 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1373 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1374 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1375 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1376 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1377 | } |
| 1378 | } |
| 1379 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1380 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1381 | { |
| 1382 | int works[NUM_LANES]; |
| 1383 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1384 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1385 | while (1) { |
| 1386 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1387 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1388 | program_timings(ctrl, channel); |
| 1389 | test_timA(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1390 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1391 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1392 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1393 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1394 | if (works[lane]) |
| 1395 | some_works = 1; |
| 1396 | else |
| 1397 | all_works = 0; |
| 1398 | } |
| 1399 | if (all_works) |
| 1400 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1401 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1402 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1403 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1404 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1405 | channel, slotrank); |
| 1406 | return MAKE_ERR; |
| 1407 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1408 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1409 | printram("4024 -= 2;\n"); |
| 1410 | continue; |
| 1411 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1412 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1413 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1414 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1415 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1416 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1417 | channel, slotrank); |
| 1418 | return MAKE_ERR; |
| 1419 | } |
| 1420 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1421 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1422 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1423 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1424 | } |
| 1425 | } |
| 1426 | return 0; |
| 1427 | } |
| 1428 | |
| 1429 | struct timA_minmax { |
| 1430 | int timA_min_high, timA_max_high; |
| 1431 | }; |
| 1432 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1433 | static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1434 | struct timA_minmax *mnmx) |
| 1435 | { |
| 1436 | int lane; |
| 1437 | mnmx->timA_min_high = 7; |
| 1438 | mnmx->timA_max_high = 0; |
| 1439 | |
| 1440 | FOR_ALL_LANES { |
| 1441 | if (mnmx->timA_min_high > |
| 1442 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1443 | mnmx->timA_min_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1444 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1445 | if (mnmx->timA_max_high < |
| 1446 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1447 | mnmx->timA_max_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1448 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1449 | } |
| 1450 | } |
| 1451 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1452 | static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1453 | struct timA_minmax *mnmx) |
| 1454 | { |
| 1455 | struct timA_minmax post; |
| 1456 | int shift_402x = 0; |
| 1457 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1458 | /* Get changed maxima */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1459 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1460 | |
| 1461 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1462 | post.timA_max_high - post.timA_min_high) |
| 1463 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1464 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1465 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1466 | post.timA_max_high - post.timA_min_high) |
| 1467 | shift_402x = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1468 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1469 | else |
| 1470 | shift_402x = 0; |
| 1471 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1472 | ctrl->timings[channel][slotrank].io_latency += shift_402x; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1473 | ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1474 | printram("4024 += %d;\n", shift_402x); |
| 1475 | printram("4028 += %d;\n", shift_402x); |
| 1476 | } |
| 1477 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1478 | /* |
| 1479 | * Compensate the skew between DQS and DQs. |
| 1480 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1481 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1482 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1483 | * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1484 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1485 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1486 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1487 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1488 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1489 | * DQ in phase the data being read is expected to alternate on every byte: |
| 1490 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1491 | * 0xFF 0x00 0xFF ... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1492 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1493 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1494 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1495 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1496 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1497 | { |
| 1498 | int channel, slotrank, lane; |
| 1499 | int err; |
| 1500 | |
| 1501 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1502 | int all_high, some_high; |
| 1503 | int upperA[NUM_LANES]; |
| 1504 | struct timA_minmax mnmx; |
| 1505 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1506 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1507 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1508 | /* DRAM command PREA */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1509 | { |
| 1510 | const struct iosav_ssq ssq = { |
| 1511 | .sp_cmd_ctrl = { |
| 1512 | .command = IOSAV_PRE, |
| 1513 | .ranksel_ap = 1, |
| 1514 | }, |
| 1515 | .subseq_ctrl = { |
| 1516 | .cmd_executions = 1, |
| 1517 | .cmd_delay_gap = 3, |
| 1518 | .post_ssq_wait = ctrl->tRP, |
| 1519 | .data_direction = SSQ_NA, |
| 1520 | }, |
| 1521 | .sp_cmd_addr = { |
| 1522 | .address = 1024, |
| 1523 | .rowbits = 6, |
| 1524 | .bank = 0, |
| 1525 | .rank = slotrank, |
| 1526 | }, |
| 1527 | }; |
| 1528 | iosav_write_ssq(channel, &ssq); |
| 1529 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1530 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1531 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1532 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1533 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1534 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1535 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1536 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1537 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1538 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1539 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1540 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1541 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1542 | all_high = 1; |
| 1543 | some_high = 0; |
| 1544 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1545 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1546 | some_high = 1; |
| 1547 | else |
| 1548 | all_high = 0; |
| 1549 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1550 | |
| 1551 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1552 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1553 | printram("4028--;\n"); |
| 1554 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1555 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1556 | upperA[lane] -= 0x40; |
| 1557 | |
| 1558 | } |
| 1559 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1560 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1561 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1562 | printram("4024++;\n"); |
| 1563 | printram("4028++;\n"); |
| 1564 | } |
| 1565 | |
| 1566 | program_timings(ctrl, channel); |
| 1567 | |
| 1568 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1569 | |
| 1570 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1571 | if (err) |
| 1572 | return err; |
| 1573 | |
| 1574 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1575 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1576 | |
| 1577 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1578 | |
| 1579 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1580 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1581 | |
| 1582 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1583 | ctrl->timings[channel][slotrank].lanes[lane].timA -= |
| 1584 | mnmx.timA_min_high * 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1585 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1586 | ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1587 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1588 | |
| 1589 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1590 | |
| 1591 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1592 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1593 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1594 | |
| 1595 | printram("final results:\n"); |
| 1596 | FOR_ALL_LANES |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1597 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1598 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1599 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1600 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1601 | |
| 1602 | toggle_io_reset(); |
| 1603 | } |
| 1604 | |
| 1605 | FOR_ALL_POPULATED_CHANNELS { |
| 1606 | program_timings(ctrl, channel); |
| 1607 | } |
| 1608 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1609 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1610 | } |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1614 | static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1615 | { |
| 1616 | int lane; |
| 1617 | |
| 1618 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1619 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1620 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1621 | } |
| 1622 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1623 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1624 | |
| 1625 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1626 | { |
| 1627 | const struct iosav_ssq ssq = { |
| 1628 | .sp_cmd_ctrl = { |
| 1629 | .command = IOSAV_ACT, |
| 1630 | .ranksel_ap = 1, |
| 1631 | }, |
| 1632 | .subseq_ctrl = { |
| 1633 | .cmd_executions = 4, |
| 1634 | .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), |
| 1635 | .post_ssq_wait = ctrl->tRCD, |
| 1636 | .data_direction = SSQ_NA, |
| 1637 | }, |
| 1638 | .sp_cmd_addr = { |
| 1639 | .address = 0, |
| 1640 | .rowbits = 6, |
| 1641 | .bank = 0, |
| 1642 | .rank = slotrank, |
| 1643 | }, |
| 1644 | .addr_update = { |
| 1645 | .inc_bank = 1, |
| 1646 | .addr_wrap = 18, |
| 1647 | }, |
| 1648 | }; |
| 1649 | iosav_write_ssq(channel, &ssq); |
| 1650 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1651 | |
| 1652 | /* DRAM command NOP */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1653 | { |
| 1654 | const struct iosav_ssq ssq = { |
| 1655 | .sp_cmd_ctrl = { |
| 1656 | .command = IOSAV_NOP, |
| 1657 | .ranksel_ap = 1, |
| 1658 | }, |
| 1659 | .subseq_ctrl = { |
| 1660 | .cmd_executions = 1, |
| 1661 | .cmd_delay_gap = 4, |
| 1662 | .post_ssq_wait = 4, |
| 1663 | .data_direction = SSQ_WR, |
| 1664 | }, |
| 1665 | .sp_cmd_addr = { |
| 1666 | .address = 8, |
| 1667 | .rowbits = 0, |
| 1668 | .bank = 0, |
| 1669 | .rank = slotrank, |
| 1670 | }, |
| 1671 | .addr_update = { |
| 1672 | .addr_wrap = 31, |
| 1673 | }, |
| 1674 | }; |
| 1675 | iosav_write_ssq(channel, &ssq); |
| 1676 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1677 | |
| 1678 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1679 | { |
| 1680 | const struct iosav_ssq ssq = { |
| 1681 | .sp_cmd_ctrl = { |
| 1682 | .command = IOSAV_WR, |
| 1683 | .ranksel_ap = 1, |
| 1684 | }, |
| 1685 | .subseq_ctrl = { |
| 1686 | .cmd_executions = 500, |
| 1687 | .cmd_delay_gap = 4, |
| 1688 | .post_ssq_wait = 4, |
| 1689 | .data_direction = SSQ_WR, |
| 1690 | }, |
| 1691 | .sp_cmd_addr = { |
| 1692 | .address = 0, |
| 1693 | .rowbits = 0, |
| 1694 | .bank = 0, |
| 1695 | .rank = slotrank, |
| 1696 | }, |
| 1697 | .addr_update = { |
| 1698 | .inc_addr_8 = 1, |
| 1699 | .addr_wrap = 18, |
| 1700 | }, |
| 1701 | }; |
| 1702 | iosav_write_ssq(channel, &ssq); |
| 1703 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1704 | |
| 1705 | /* DRAM command NOP */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1706 | { |
| 1707 | const struct iosav_ssq ssq = { |
| 1708 | .sp_cmd_ctrl = { |
| 1709 | .command = IOSAV_NOP, |
| 1710 | .ranksel_ap = 1, |
| 1711 | }, |
| 1712 | .subseq_ctrl = { |
| 1713 | .cmd_executions = 1, |
| 1714 | .cmd_delay_gap = 3, |
| 1715 | .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, |
| 1716 | .data_direction = SSQ_WR, |
| 1717 | }, |
| 1718 | .sp_cmd_addr = { |
| 1719 | .address = 8, |
| 1720 | .rowbits = 0, |
| 1721 | .bank = 0, |
| 1722 | .rank = slotrank, |
| 1723 | }, |
| 1724 | .addr_update = { |
| 1725 | .addr_wrap = 31, |
| 1726 | }, |
| 1727 | }; |
| 1728 | iosav_write_ssq(channel, &ssq); |
| 1729 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1730 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1731 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1732 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1733 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1734 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1735 | |
| 1736 | /* DRAM command PREA */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1737 | { |
| 1738 | const struct iosav_ssq ssq = { |
| 1739 | .sp_cmd_ctrl = { |
| 1740 | .command = IOSAV_PRE, |
| 1741 | .ranksel_ap = 1, |
| 1742 | }, |
| 1743 | .subseq_ctrl = { |
| 1744 | .cmd_executions = 1, |
| 1745 | .cmd_delay_gap = 3, |
| 1746 | .post_ssq_wait = ctrl->tRP, |
| 1747 | .data_direction = SSQ_NA, |
| 1748 | }, |
| 1749 | .sp_cmd_addr = { |
| 1750 | .address = 1024, |
| 1751 | .rowbits = 6, |
| 1752 | .bank = 0, |
| 1753 | .rank = slotrank, |
| 1754 | }, |
| 1755 | .addr_update = { |
| 1756 | .addr_wrap = 18, |
| 1757 | }, |
| 1758 | }; |
| 1759 | iosav_write_ssq(channel, &ssq); |
| 1760 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1761 | |
| 1762 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1763 | { |
| 1764 | const struct iosav_ssq ssq = { |
| 1765 | .sp_cmd_ctrl = { |
| 1766 | .command = IOSAV_ACT, |
| 1767 | .ranksel_ap = 1, |
| 1768 | }, |
| 1769 | .subseq_ctrl = { |
| 1770 | .cmd_executions = 8, |
| 1771 | .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), |
| 1772 | .post_ssq_wait = ctrl->CAS, |
| 1773 | .data_direction = SSQ_NA, |
| 1774 | }, |
| 1775 | .sp_cmd_addr = { |
| 1776 | .address = 0, |
| 1777 | .rowbits = 6, |
| 1778 | .bank = 0, |
| 1779 | .rank = slotrank, |
| 1780 | }, |
| 1781 | .addr_update = { |
| 1782 | .inc_bank = 1, |
| 1783 | .addr_wrap = 18, |
| 1784 | }, |
| 1785 | }; |
| 1786 | iosav_write_ssq(channel, &ssq); |
| 1787 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1788 | |
| 1789 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1790 | { |
| 1791 | const struct iosav_ssq ssq = { |
| 1792 | .sp_cmd_ctrl = { |
| 1793 | .command = IOSAV_RD, |
| 1794 | .ranksel_ap = 1, |
| 1795 | }, |
| 1796 | .subseq_ctrl = { |
| 1797 | .cmd_executions = 500, |
| 1798 | .cmd_delay_gap = 4, |
| 1799 | .post_ssq_wait = MAX(ctrl->tRTP, 8), |
| 1800 | .data_direction = SSQ_RD, |
| 1801 | }, |
| 1802 | .sp_cmd_addr = { |
| 1803 | .address = 0, |
| 1804 | .rowbits = 0, |
| 1805 | .bank = 0, |
| 1806 | .rank = slotrank, |
| 1807 | }, |
| 1808 | .addr_update = { |
| 1809 | .inc_addr_8 = 1, |
| 1810 | .addr_wrap = 18, |
| 1811 | }, |
| 1812 | }; |
| 1813 | iosav_write_ssq(channel, &ssq); |
| 1814 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1815 | |
| 1816 | /* DRAM command PREA */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1817 | { |
| 1818 | const struct iosav_ssq ssq = { |
| 1819 | .sp_cmd_ctrl = { |
| 1820 | .command = IOSAV_PRE, |
| 1821 | .ranksel_ap = 1, |
| 1822 | }, |
| 1823 | .subseq_ctrl = { |
| 1824 | .cmd_executions = 1, |
| 1825 | .cmd_delay_gap = 3, |
| 1826 | .post_ssq_wait = ctrl->tRP, |
| 1827 | .data_direction = SSQ_NA, |
| 1828 | }, |
| 1829 | .sp_cmd_addr = { |
| 1830 | .address = 1024, |
| 1831 | .rowbits = 6, |
| 1832 | .bank = 0, |
| 1833 | .rank = slotrank, |
| 1834 | }, |
| 1835 | .addr_update = { |
| 1836 | .addr_wrap = 18, |
| 1837 | }, |
| 1838 | }; |
| 1839 | iosav_write_ssq(channel, &ssq); |
| 1840 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1841 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1842 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1843 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1844 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1845 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1846 | } |
| 1847 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1848 | static void timC_threshold_process(int *data, const int count) |
| 1849 | { |
| 1850 | int min = data[0]; |
| 1851 | int max = min; |
| 1852 | int i; |
| 1853 | for (i = 1; i < count; i++) { |
| 1854 | if (min > data[i]) |
| 1855 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1856 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1857 | if (max < data[i]) |
| 1858 | max = data[i]; |
| 1859 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1860 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1861 | for (i = 0; i < count; i++) |
| 1862 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1863 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1864 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1865 | } |
| 1866 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1867 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1868 | { |
| 1869 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1870 | int stats[NUM_LANES][MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1871 | int lane; |
| 1872 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1873 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1874 | |
| 1875 | /* DRAM command PREA */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1876 | { |
| 1877 | const struct iosav_ssq ssq = { |
| 1878 | .sp_cmd_ctrl = { |
| 1879 | .command = IOSAV_PRE, |
| 1880 | .ranksel_ap = 1, |
| 1881 | }, |
| 1882 | .subseq_ctrl = { |
| 1883 | .cmd_executions = 1, |
| 1884 | .cmd_delay_gap = 3, |
| 1885 | .post_ssq_wait = ctrl->tRP, |
| 1886 | .data_direction = SSQ_NA, |
| 1887 | }, |
| 1888 | .sp_cmd_addr = { |
| 1889 | .address = 1024, |
| 1890 | .rowbits = 6, |
| 1891 | .bank = 0, |
| 1892 | .rank = slotrank, |
| 1893 | }, |
| 1894 | .addr_update = { |
| 1895 | .addr_wrap = 18, |
| 1896 | }, |
| 1897 | }; |
| 1898 | iosav_write_ssq(channel, &ssq); |
| 1899 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1900 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1901 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 1902 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1903 | |
| 1904 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1905 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1906 | program_timings(ctrl, channel); |
| 1907 | |
| 1908 | test_timC(ctrl, channel, slotrank); |
| 1909 | |
| 1910 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1911 | stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1912 | } |
| 1913 | } |
| 1914 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1915 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1916 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1917 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1918 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1919 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1920 | /* |
| 1921 | * With command training not being done yet, the lane can be erroneous. |
| 1922 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1923 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1924 | timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1925 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1926 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1927 | if (rn.all || rn.length < 8) { |
| 1928 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1929 | return MAKE_ERR; |
| 1930 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1931 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1932 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1933 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1934 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1935 | } |
| 1936 | return 0; |
| 1937 | } |
| 1938 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1939 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1940 | { |
| 1941 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1942 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1943 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1944 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1945 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1946 | return ret; |
| 1947 | } |
| 1948 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1949 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1950 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1951 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1952 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1953 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1954 | for (j = 0; j < 16; j++) |
| 1955 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1956 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1957 | sfence(); |
| 1958 | } |
| 1959 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1960 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1961 | { |
| 1962 | int ret = 0; |
| 1963 | int channel; |
| 1964 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1965 | return ret; |
| 1966 | } |
| 1967 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1968 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1969 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1970 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1971 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1972 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1973 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1974 | for (j = 0; j < 16; j++) |
| 1975 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1976 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1977 | for (j = 0; j < 16; j++) |
| 1978 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1979 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1980 | sfence(); |
| 1981 | } |
| 1982 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1983 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1984 | { |
| 1985 | int channel, slotrank, lane; |
| 1986 | |
| 1987 | FOR_ALL_POPULATED_CHANNELS { |
| 1988 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1989 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1990 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1991 | } |
| 1992 | |
| 1993 | program_timings(ctrl, channel); |
| 1994 | |
| 1995 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1996 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1997 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 1998 | /* |
| 1999 | * DRAM command MRS |
| 2000 | * |
| 2001 | * Write MR3 MPR enable. |
| 2002 | * In this mode only RD and RDA are allowed, |
| 2003 | * and all reads return a predefined pattern. |
| 2004 | */ |
| 2005 | { |
| 2006 | const struct iosav_ssq ssq = { |
| 2007 | .sp_cmd_ctrl = { |
| 2008 | .command = IOSAV_MRS, |
| 2009 | .ranksel_ap = 1, |
| 2010 | }, |
| 2011 | .subseq_ctrl = { |
| 2012 | .cmd_executions = 1, |
| 2013 | .cmd_delay_gap = 3, |
| 2014 | .post_ssq_wait = ctrl->tMOD, |
| 2015 | .data_direction = SSQ_NA, |
| 2016 | }, |
| 2017 | .sp_cmd_addr = { |
| 2018 | .address = 4, |
| 2019 | .rowbits = 6, |
| 2020 | .bank = 3, |
| 2021 | .rank = slotrank, |
| 2022 | }, |
| 2023 | }; |
| 2024 | iosav_write_ssq(channel, &ssq); |
| 2025 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2026 | |
| 2027 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2028 | { |
| 2029 | const struct iosav_ssq ssq = { |
| 2030 | .sp_cmd_ctrl = { |
| 2031 | .command = IOSAV_RD, |
| 2032 | .ranksel_ap = 1, |
| 2033 | }, |
| 2034 | .subseq_ctrl = { |
| 2035 | .cmd_executions = 3, |
| 2036 | .cmd_delay_gap = 4, |
| 2037 | .post_ssq_wait = 4, |
| 2038 | .data_direction = SSQ_RD, |
| 2039 | }, |
| 2040 | .sp_cmd_addr = { |
| 2041 | .address = 0, |
| 2042 | .rowbits = 0, |
| 2043 | .bank = 0, |
| 2044 | .rank = slotrank, |
| 2045 | }, |
| 2046 | }; |
| 2047 | iosav_write_ssq(channel, &ssq); |
| 2048 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2049 | |
| 2050 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2051 | { |
| 2052 | const struct iosav_ssq ssq = { |
| 2053 | .sp_cmd_ctrl = { |
| 2054 | .command = IOSAV_RD, |
| 2055 | .ranksel_ap = 1, |
| 2056 | }, |
| 2057 | .subseq_ctrl = { |
| 2058 | .cmd_executions = 1, |
| 2059 | .cmd_delay_gap = 4, |
| 2060 | .post_ssq_wait = ctrl->CAS + 8, |
| 2061 | .data_direction = SSQ_NA, |
| 2062 | }, |
| 2063 | .sp_cmd_addr = { |
| 2064 | .address = 0, |
| 2065 | .rowbits = 6, |
| 2066 | .bank = 0, |
| 2067 | .rank = slotrank, |
| 2068 | }, |
| 2069 | }; |
| 2070 | iosav_write_ssq(channel, &ssq); |
| 2071 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2072 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2073 | /* |
| 2074 | * DRAM command MRS |
| 2075 | * |
| 2076 | * Write MR3 MPR disable. |
| 2077 | */ |
| 2078 | { |
| 2079 | const struct iosav_ssq ssq = { |
| 2080 | .sp_cmd_ctrl = { |
| 2081 | .command = IOSAV_MRS, |
| 2082 | .ranksel_ap = 1, |
| 2083 | }, |
| 2084 | .subseq_ctrl = { |
| 2085 | .cmd_executions = 1, |
| 2086 | .cmd_delay_gap = 3, |
| 2087 | .post_ssq_wait = ctrl->tMOD, |
| 2088 | .data_direction = SSQ_NA, |
| 2089 | }, |
| 2090 | .sp_cmd_addr = { |
| 2091 | .address = 0, |
| 2092 | .rowbits = 6, |
| 2093 | .bank = 3, |
| 2094 | .rank = slotrank, |
| 2095 | }, |
| 2096 | }; |
| 2097 | iosav_write_ssq(channel, &ssq); |
| 2098 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2099 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2100 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2101 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2102 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2103 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2104 | } |
| 2105 | |
| 2106 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2107 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 2108 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2109 | } |
| 2110 | |
| 2111 | program_timings(ctrl, channel); |
| 2112 | |
| 2113 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2114 | wait_for_iosav(channel); |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2115 | |
| 2116 | /* |
| 2117 | * DRAM command MRS |
| 2118 | * |
| 2119 | * Write MR3 MPR enable. |
| 2120 | * In this mode only RD and RDA are allowed, |
| 2121 | * and all reads return a predefined pattern. |
| 2122 | */ |
| 2123 | { |
| 2124 | const struct iosav_ssq ssq = { |
| 2125 | .sp_cmd_ctrl = { |
| 2126 | .command = IOSAV_MRS, |
| 2127 | .ranksel_ap = 1, |
| 2128 | }, |
| 2129 | .subseq_ctrl = { |
| 2130 | .cmd_executions = 1, |
| 2131 | .cmd_delay_gap = 3, |
| 2132 | .post_ssq_wait = ctrl->tMOD, |
| 2133 | .data_direction = SSQ_NA, |
| 2134 | }, |
| 2135 | .sp_cmd_addr = { |
| 2136 | .address = 4, |
| 2137 | .rowbits = 6, |
| 2138 | .bank = 3, |
| 2139 | .rank = slotrank, |
| 2140 | }, |
| 2141 | }; |
| 2142 | iosav_write_ssq(channel, &ssq); |
| 2143 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2144 | |
| 2145 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2146 | { |
| 2147 | const struct iosav_ssq ssq = { |
| 2148 | .sp_cmd_ctrl = { |
| 2149 | .command = IOSAV_RD, |
| 2150 | .ranksel_ap = 1, |
| 2151 | }, |
| 2152 | .subseq_ctrl = { |
| 2153 | .cmd_executions = 3, |
| 2154 | .cmd_delay_gap = 4, |
| 2155 | .post_ssq_wait = 4, |
| 2156 | .data_direction = SSQ_RD, |
| 2157 | }, |
| 2158 | .sp_cmd_addr = { |
| 2159 | .address = 0, |
| 2160 | .rowbits = 0, |
| 2161 | .bank = 0, |
| 2162 | .rank = slotrank, |
| 2163 | }, |
| 2164 | }; |
| 2165 | iosav_write_ssq(channel, &ssq); |
| 2166 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2167 | |
| 2168 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2169 | { |
| 2170 | const struct iosav_ssq ssq = { |
| 2171 | .sp_cmd_ctrl = { |
| 2172 | .command = IOSAV_RD, |
| 2173 | .ranksel_ap = 1, |
| 2174 | }, |
| 2175 | .subseq_ctrl = { |
| 2176 | .cmd_executions = 1, |
| 2177 | .cmd_delay_gap = 4, |
| 2178 | .post_ssq_wait = ctrl->CAS + 8, |
| 2179 | .data_direction = SSQ_NA, |
| 2180 | }, |
| 2181 | .sp_cmd_addr = { |
| 2182 | .address = 0, |
| 2183 | .rowbits = 6, |
| 2184 | .bank = 0, |
| 2185 | .rank = slotrank, |
| 2186 | }, |
| 2187 | }; |
| 2188 | iosav_write_ssq(channel, &ssq); |
| 2189 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2190 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2191 | /* |
| 2192 | * DRAM command MRS |
| 2193 | * |
| 2194 | * Write MR3 MPR disable. |
| 2195 | */ |
| 2196 | { |
| 2197 | const struct iosav_ssq ssq = { |
| 2198 | .sp_cmd_ctrl = { |
| 2199 | .command = IOSAV_MRS, |
| 2200 | .ranksel_ap = 1, |
| 2201 | }, |
| 2202 | .subseq_ctrl = { |
| 2203 | .cmd_executions = 1, |
| 2204 | .cmd_delay_gap = 3, |
| 2205 | .post_ssq_wait = ctrl->tMOD, |
| 2206 | .data_direction = SSQ_NA, |
| 2207 | }, |
| 2208 | .sp_cmd_addr = { |
| 2209 | .address = 0, |
| 2210 | .rowbits = 6, |
| 2211 | .bank = 3, |
| 2212 | .rank = slotrank, |
| 2213 | }, |
| 2214 | }; |
| 2215 | iosav_write_ssq(channel, &ssq); |
| 2216 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2217 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2218 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2219 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2220 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2221 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2222 | } |
| 2223 | } |
| 2224 | } |
| 2225 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2226 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2227 | { |
| 2228 | /* enable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2229 | write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2230 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2231 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2232 | /* DRAM command NOP */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2233 | { |
| 2234 | const struct iosav_ssq ssq = { |
| 2235 | .sp_cmd_ctrl = { |
| 2236 | .command = IOSAV_NOP, |
| 2237 | .ranksel_ap = 1, |
| 2238 | }, |
| 2239 | .subseq_ctrl = { |
| 2240 | .cmd_executions = 1, |
| 2241 | .cmd_delay_gap = 3, |
| 2242 | .post_ssq_wait = ctrl->CWL + ctrl->tWLO, |
| 2243 | .data_direction = SSQ_WR, |
| 2244 | }, |
| 2245 | .sp_cmd_addr = { |
| 2246 | .address = 8, |
| 2247 | .rowbits = 0, |
| 2248 | .bank = 0, |
| 2249 | .rank = slotrank, |
| 2250 | }, |
| 2251 | }; |
| 2252 | iosav_write_ssq(channel, &ssq); |
| 2253 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2254 | |
| 2255 | /* DRAM command NOP */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2256 | { |
| 2257 | const struct iosav_ssq ssq = { |
| 2258 | .sp_cmd_ctrl = { |
| 2259 | .command = IOSAV_NOP_ALT, |
| 2260 | .ranksel_ap = 1, |
| 2261 | }, |
| 2262 | .subseq_ctrl = { |
| 2263 | .cmd_executions = 1, |
| 2264 | .cmd_delay_gap = 3, |
| 2265 | .post_ssq_wait = ctrl->CAS + 38, |
| 2266 | .data_direction = SSQ_RD, |
| 2267 | }, |
| 2268 | .sp_cmd_addr = { |
| 2269 | .address = 4, |
| 2270 | .rowbits = 0, |
| 2271 | .bank = 0, |
| 2272 | .rank = slotrank, |
| 2273 | }, |
| 2274 | }; |
| 2275 | iosav_write_ssq(channel, &ssq); |
| 2276 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2277 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2278 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2279 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2280 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2281 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2282 | |
| 2283 | /* disable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2284 | write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2285 | } |
| 2286 | |
| 2287 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 2288 | { |
| 2289 | int timB; |
| 2290 | int statistics[NUM_LANES][128]; |
| 2291 | int lane; |
| 2292 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2293 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2294 | |
| 2295 | for (timB = 0; timB < 128; timB++) { |
| 2296 | FOR_ALL_LANES { |
| 2297 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 2298 | } |
| 2299 | program_timings(ctrl, channel); |
| 2300 | |
| 2301 | test_timB(ctrl, channel, slotrank); |
| 2302 | |
| 2303 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2304 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 2305 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 2306 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2307 | } |
| 2308 | } |
| 2309 | FOR_ALL_LANES { |
| 2310 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2311 | /* |
| 2312 | * timC is a direct function of timB's 6 LSBs. Some tests increments the value |
| 2313 | * of timB by a small value, which might cause the 6-bit value to overflow if |
| 2314 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 2315 | * to overflow, to make sure it won't overflow while running tests and bricks |
| 2316 | * the system due to a non matching timC. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2317 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2318 | * TODO: find out why some tests (edge write discovery) increment timB. |
| 2319 | */ |
| 2320 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2321 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2322 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2323 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2324 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2325 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 2326 | if (rn.all) { |
| 2327 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 2328 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2329 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2330 | return MAKE_ERR; |
| 2331 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2332 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2333 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2334 | } |
| 2335 | return 0; |
| 2336 | } |
| 2337 | |
| 2338 | static int get_timB_high_adjust(u64 val) |
| 2339 | { |
| 2340 | int i; |
| 2341 | |
| 2342 | /* good */ |
| 2343 | if (val == 0xffffffffffffffffLL) |
| 2344 | return 0; |
| 2345 | |
| 2346 | if (val >= 0xf000000000000000LL) { |
| 2347 | /* needs negative adjustment */ |
| 2348 | for (i = 0; i < 8; i++) |
| 2349 | if (val << (8 * (7 - i) + 4)) |
| 2350 | return -i; |
| 2351 | } else { |
| 2352 | /* needs positive adjustment */ |
| 2353 | for (i = 0; i < 8; i++) |
| 2354 | if (val >> (8 * (7 - i) + 4)) |
| 2355 | return i; |
| 2356 | } |
| 2357 | return 8; |
| 2358 | } |
| 2359 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2360 | static void adjust_high_timB(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2361 | { |
| 2362 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2363 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2364 | FOR_ALL_POPULATED_CHANNELS { |
| 2365 | fill_pattern1(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2366 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2367 | } |
| 2368 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2369 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2370 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2371 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2372 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2373 | |
| 2374 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2375 | { |
| 2376 | const struct iosav_ssq ssq = { |
| 2377 | .sp_cmd_ctrl = { |
| 2378 | .command = IOSAV_ACT, |
| 2379 | .ranksel_ap = 1, |
| 2380 | }, |
| 2381 | .subseq_ctrl = { |
| 2382 | .cmd_executions = 1, |
| 2383 | .cmd_delay_gap = 3, |
| 2384 | .post_ssq_wait = ctrl->tRCD, |
| 2385 | .data_direction = SSQ_NA, |
| 2386 | }, |
| 2387 | .sp_cmd_addr = { |
| 2388 | .address = 0, |
| 2389 | .rowbits = 6, |
| 2390 | .bank = 0, |
| 2391 | .rank = slotrank, |
| 2392 | }, |
| 2393 | }; |
| 2394 | iosav_write_ssq(channel, &ssq); |
| 2395 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2396 | |
| 2397 | /* DRAM command NOP */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2398 | { |
| 2399 | const struct iosav_ssq ssq = { |
| 2400 | .sp_cmd_ctrl = { |
| 2401 | .command = IOSAV_NOP, |
| 2402 | .ranksel_ap = 1, |
| 2403 | }, |
| 2404 | .subseq_ctrl = { |
| 2405 | .cmd_executions = 1, |
| 2406 | .cmd_delay_gap = 3, |
| 2407 | .post_ssq_wait = 4, |
| 2408 | .data_direction = SSQ_WR, |
| 2409 | }, |
| 2410 | .sp_cmd_addr = { |
| 2411 | .address = 8, |
| 2412 | .rowbits = 0, |
| 2413 | .bank = 0, |
| 2414 | .rank = slotrank, |
| 2415 | }, |
| 2416 | .addr_update = { |
| 2417 | .addr_wrap = 31, |
| 2418 | }, |
| 2419 | }; |
| 2420 | iosav_write_ssq(channel, &ssq); |
| 2421 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2422 | |
| 2423 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2424 | { |
| 2425 | const struct iosav_ssq ssq = { |
| 2426 | .sp_cmd_ctrl = { |
| 2427 | .command = IOSAV_WR, |
| 2428 | .ranksel_ap = 1, |
| 2429 | }, |
| 2430 | .subseq_ctrl = { |
| 2431 | .cmd_executions = 3, |
| 2432 | .cmd_delay_gap = 4, |
| 2433 | .post_ssq_wait = 4, |
| 2434 | .data_direction = SSQ_WR, |
| 2435 | }, |
| 2436 | .sp_cmd_addr = { |
| 2437 | .address = 0, |
| 2438 | .rowbits = 0, |
| 2439 | .bank = 0, |
| 2440 | .rank = slotrank, |
| 2441 | }, |
| 2442 | .addr_update = { |
| 2443 | .inc_addr_8 = 1, |
| 2444 | .addr_wrap = 31, |
| 2445 | }, |
| 2446 | }; |
| 2447 | iosav_write_ssq(channel, &ssq); |
| 2448 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2449 | |
| 2450 | /* DRAM command NOP */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2451 | { |
| 2452 | const struct iosav_ssq ssq = { |
| 2453 | .sp_cmd_ctrl = { |
| 2454 | .command = IOSAV_NOP, |
| 2455 | .ranksel_ap = 1, |
| 2456 | }, |
| 2457 | .subseq_ctrl = { |
| 2458 | .cmd_executions = 1, |
| 2459 | .cmd_delay_gap = 3, |
| 2460 | .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 5, |
| 2461 | .data_direction = SSQ_WR, |
| 2462 | }, |
| 2463 | .sp_cmd_addr = { |
| 2464 | .address = 8, |
| 2465 | .rowbits = 0, |
| 2466 | .bank = 0, |
| 2467 | .rank = slotrank, |
| 2468 | }, |
| 2469 | .addr_update = { |
| 2470 | .addr_wrap = 31, |
| 2471 | }, |
| 2472 | }; |
| 2473 | iosav_write_ssq(channel, &ssq); |
| 2474 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2475 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2476 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2477 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2478 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2479 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2480 | |
| 2481 | /* DRAM command PREA */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2482 | { |
| 2483 | const struct iosav_ssq ssq = { |
| 2484 | .sp_cmd_ctrl = { |
| 2485 | .command = IOSAV_PRE, |
| 2486 | .ranksel_ap = 1, |
| 2487 | }, |
| 2488 | .subseq_ctrl = { |
| 2489 | .cmd_executions = 1, |
| 2490 | .cmd_delay_gap = 3, |
| 2491 | .post_ssq_wait = ctrl->tRP, |
| 2492 | .data_direction = SSQ_NA, |
| 2493 | }, |
| 2494 | .sp_cmd_addr = { |
| 2495 | .address = 1024, |
| 2496 | .rowbits = 6, |
| 2497 | .bank = 0, |
| 2498 | .rank = slotrank, |
| 2499 | }, |
| 2500 | .addr_update = { |
| 2501 | .addr_wrap = 18, |
| 2502 | }, |
| 2503 | }; |
| 2504 | iosav_write_ssq(channel, &ssq); |
| 2505 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2506 | |
| 2507 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2508 | { |
| 2509 | const struct iosav_ssq ssq = { |
| 2510 | .sp_cmd_ctrl = { |
| 2511 | .command = IOSAV_ACT, |
| 2512 | .ranksel_ap = 1, |
| 2513 | }, |
| 2514 | .subseq_ctrl = { |
| 2515 | .cmd_executions = 1, |
| 2516 | .cmd_delay_gap = 3, |
| 2517 | .post_ssq_wait = ctrl->tRCD, |
| 2518 | .data_direction = SSQ_NA, |
| 2519 | }, |
| 2520 | .sp_cmd_addr = { |
| 2521 | .address = 0, |
| 2522 | .rowbits = 6, |
| 2523 | .bank = 0, |
| 2524 | .rank = slotrank, |
| 2525 | }, |
| 2526 | }; |
| 2527 | iosav_write_ssq(channel, &ssq); |
| 2528 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2529 | |
| 2530 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2531 | { |
| 2532 | const struct iosav_ssq ssq = { |
| 2533 | .sp_cmd_ctrl = { |
| 2534 | .command = IOSAV_RD, |
| 2535 | .ranksel_ap = 3, |
| 2536 | }, |
| 2537 | .subseq_ctrl = { |
| 2538 | .cmd_executions = 1, |
| 2539 | .cmd_delay_gap = 3, |
| 2540 | .post_ssq_wait = ctrl->tRP + |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2541 | ctrl->timings[channel][slotrank].roundtrip_latency + |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2542 | ctrl->timings[channel][slotrank].io_latency, |
| 2543 | .data_direction = SSQ_RD, |
| 2544 | }, |
| 2545 | .sp_cmd_addr = { |
| 2546 | .address = 8, |
| 2547 | .rowbits = 6, |
| 2548 | .bank = 0, |
| 2549 | .rank = slotrank, |
| 2550 | }, |
| 2551 | }; |
| 2552 | iosav_write_ssq(channel, &ssq); |
| 2553 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2554 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2555 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2556 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2557 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2558 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2559 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2560 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 2561 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2562 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2563 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 2564 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 2565 | get_timB_high_adjust(res) * 64; |
| 2566 | |
| 2567 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2568 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 2569 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2570 | } |
| 2571 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2572 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2573 | } |
| 2574 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2575 | static void write_op(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2576 | { |
| 2577 | int slotrank; |
| 2578 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2579 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2580 | |
| 2581 | /* choose an existing rank. */ |
| 2582 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2583 | |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 2584 | /* DRAM command ZQCS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2585 | { |
| 2586 | const struct iosav_ssq ssq = { |
| 2587 | .sp_cmd_ctrl = { |
| 2588 | .command = IOSAV_ZQCS, |
| 2589 | }, |
| 2590 | .subseq_ctrl = { |
| 2591 | .cmd_executions = 1, |
| 2592 | .cmd_delay_gap = 4, |
| 2593 | .post_ssq_wait = 4, |
| 2594 | .data_direction = SSQ_NA, |
| 2595 | }, |
| 2596 | .sp_cmd_addr = { |
| 2597 | .address = 0, |
| 2598 | .rowbits = 6, |
| 2599 | .bank = 0, |
| 2600 | .rank = slotrank, |
| 2601 | }, |
| 2602 | .addr_update = { |
| 2603 | .addr_wrap = 31, |
| 2604 | }, |
| 2605 | }; |
| 2606 | iosav_write_ssq(channel, &ssq); |
| 2607 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2608 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2609 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2610 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2611 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2612 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2613 | } |
| 2614 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2615 | /* |
| 2616 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2617 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2618 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 2619 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 2620 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 2621 | * CLK/ADDR/CMD signals have the same routing delay. |
| 2622 | * |
| 2623 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 2624 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 2625 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2626 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2627 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2628 | { |
| 2629 | int channel, slotrank, lane; |
| 2630 | int err; |
| 2631 | |
| 2632 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2633 | MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2634 | |
| 2635 | FOR_ALL_POPULATED_CHANNELS { |
| 2636 | write_op(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2637 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2638 | } |
| 2639 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2640 | /* Refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2641 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2642 | FOR_ALL_POPULATED_CHANNELS { |
| 2643 | write_op(ctrl, channel); |
| 2644 | } |
| 2645 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2646 | /* Enable write leveling on all ranks |
| 2647 | Disable all DQ outputs |
| 2648 | Only NOP is allowed in this mode */ |
| 2649 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 2650 | write_mrreg(ctrl, channel, slotrank, 1, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2651 | make_mr1(ctrl, slotrank, channel) | 0x1080); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2652 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2653 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2654 | |
| 2655 | toggle_io_reset(); |
| 2656 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2657 | /* Set any valid value for timB, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2658 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2659 | err = discover_timB(ctrl, channel, slotrank); |
| 2660 | if (err) |
| 2661 | return err; |
| 2662 | } |
| 2663 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2664 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2665 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2666 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2667 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2668 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2669 | |
| 2670 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2671 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2672 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2673 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2674 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2675 | |
| 2676 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2677 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); |
| 2678 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 2679 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2680 | |
| 2681 | /* DRAM command ZQCS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2682 | { |
| 2683 | const struct iosav_ssq ssq = { |
| 2684 | .sp_cmd_ctrl = { |
| 2685 | .command = IOSAV_ZQCS, |
| 2686 | }, |
| 2687 | .subseq_ctrl = { |
| 2688 | .cmd_executions = 1, |
| 2689 | .cmd_delay_gap = 4, |
| 2690 | .post_ssq_wait = 101, |
| 2691 | .data_direction = SSQ_NA, |
| 2692 | }, |
| 2693 | .sp_cmd_addr = { |
| 2694 | .address = 0, |
| 2695 | .rowbits = 6, |
| 2696 | .bank = 0, |
| 2697 | .rank = 0, |
| 2698 | }, |
| 2699 | .addr_update = { |
| 2700 | .addr_wrap = 31, |
| 2701 | }, |
| 2702 | }; |
| 2703 | iosav_write_ssq(channel, &ssq); |
| 2704 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2705 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2706 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2707 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2708 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2709 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2710 | } |
| 2711 | |
| 2712 | toggle_io_reset(); |
| 2713 | |
| 2714 | printram("CPE\n"); |
| 2715 | precharge(ctrl); |
| 2716 | printram("CPF\n"); |
| 2717 | |
| 2718 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2719 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2720 | } |
| 2721 | |
| 2722 | FOR_ALL_POPULATED_CHANNELS { |
| 2723 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2724 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2725 | } |
| 2726 | |
| 2727 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2728 | err = discover_timC(ctrl, channel, slotrank); |
| 2729 | if (err) |
| 2730 | return err; |
| 2731 | } |
| 2732 | |
| 2733 | FOR_ALL_POPULATED_CHANNELS |
| 2734 | program_timings(ctrl, channel); |
| 2735 | |
| 2736 | /* measure and adjust timB timings */ |
| 2737 | adjust_high_timB(ctrl); |
| 2738 | |
| 2739 | FOR_ALL_POPULATED_CHANNELS |
| 2740 | program_timings(ctrl, channel); |
| 2741 | |
| 2742 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2743 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2744 | } |
| 2745 | return 0; |
| 2746 | } |
| 2747 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2748 | static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2749 | { |
| 2750 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2751 | int timC_delta; |
| 2752 | int lanes_ok = 0; |
| 2753 | int ctr = 0; |
| 2754 | int lane; |
| 2755 | |
| 2756 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2757 | FOR_ALL_LANES { |
| 2758 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2759 | saved_rt.lanes[lane].timC + timC_delta; |
| 2760 | } |
| 2761 | program_timings(ctrl, channel); |
| 2762 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2763 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2764 | } |
| 2765 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2766 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2767 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2768 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2769 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2770 | { |
| 2771 | const struct iosav_ssq ssq = { |
| 2772 | .sp_cmd_ctrl = { |
| 2773 | .command = IOSAV_ACT, |
| 2774 | .ranksel_ap = 1, |
| 2775 | }, |
| 2776 | .subseq_ctrl = { |
| 2777 | .cmd_executions = 8, |
| 2778 | .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), |
| 2779 | .post_ssq_wait = ctrl->tRCD, |
| 2780 | .data_direction = SSQ_NA, |
| 2781 | }, |
| 2782 | .sp_cmd_addr = { |
| 2783 | .address = ctr, |
| 2784 | .rowbits = 6, |
| 2785 | .bank = 0, |
| 2786 | .rank = slotrank, |
| 2787 | }, |
| 2788 | .addr_update = { |
| 2789 | .inc_bank = 1, |
| 2790 | .addr_wrap = 18, |
| 2791 | }, |
| 2792 | }; |
| 2793 | iosav_write_ssq(channel, &ssq); |
| 2794 | } |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 2795 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2796 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2797 | { |
| 2798 | const struct iosav_ssq ssq = { |
| 2799 | .sp_cmd_ctrl = { |
| 2800 | .command = IOSAV_WR, |
| 2801 | .ranksel_ap = 1, |
| 2802 | }, |
| 2803 | .subseq_ctrl = { |
| 2804 | .cmd_executions = 32, |
| 2805 | .cmd_delay_gap = 4, |
| 2806 | .post_ssq_wait = ctrl->CWL + ctrl->tWTR + 8, |
| 2807 | .data_direction = SSQ_WR, |
| 2808 | }, |
| 2809 | .sp_cmd_addr = { |
| 2810 | .address = 0, |
| 2811 | .rowbits = 0, |
| 2812 | .bank = 0, |
| 2813 | .rank = slotrank, |
| 2814 | }, |
| 2815 | .addr_update = { |
| 2816 | .inc_addr_8 = 1, |
| 2817 | .addr_wrap = 18, |
| 2818 | .lfsr_upd = 3, |
| 2819 | .lfsr_xors = 2, |
| 2820 | }, |
| 2821 | }; |
| 2822 | iosav_write_ssq(channel, &ssq); |
| 2823 | } |
| 2824 | /* FIXME: Hardcoded subsequence index */ |
Angel Pons | c36cd07 | 2020-05-02 16:51:39 +0200 | [diff] [blame] | 2825 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2826 | |
| 2827 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2828 | { |
| 2829 | const struct iosav_ssq ssq = { |
| 2830 | .sp_cmd_ctrl = { |
| 2831 | .command = IOSAV_RD, |
| 2832 | .ranksel_ap = 1, |
| 2833 | }, |
| 2834 | .subseq_ctrl = { |
| 2835 | .cmd_executions = 32, |
| 2836 | .cmd_delay_gap = 4, |
| 2837 | .post_ssq_wait = MAX(ctrl->tRTP, 8), |
| 2838 | .data_direction = SSQ_RD, |
| 2839 | }, |
| 2840 | .sp_cmd_addr = { |
| 2841 | .address = 0, |
| 2842 | .rowbits = 0, |
| 2843 | .bank = 0, |
| 2844 | .rank = slotrank, |
| 2845 | }, |
| 2846 | .addr_update = { |
| 2847 | .inc_addr_8 = 1, |
| 2848 | .addr_wrap = 18, |
| 2849 | .lfsr_upd = 3, |
| 2850 | .lfsr_xors = 2, |
| 2851 | }, |
| 2852 | }; |
| 2853 | iosav_write_ssq(channel, &ssq); |
| 2854 | } |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2855 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2856 | /* FIXME: Hardcoded subsequence index */ |
Angel Pons | c36cd07 | 2020-05-02 16:51:39 +0200 | [diff] [blame] | 2857 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2858 | |
| 2859 | /* DRAM command PRE */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2860 | { |
| 2861 | const struct iosav_ssq ssq = { |
| 2862 | .sp_cmd_ctrl = { |
| 2863 | .command = IOSAV_PRE, |
| 2864 | .ranksel_ap = 1, |
| 2865 | }, |
| 2866 | .subseq_ctrl = { |
| 2867 | .cmd_executions = 1, |
| 2868 | .cmd_delay_gap = 4, |
| 2869 | .post_ssq_wait = 15, |
| 2870 | .data_direction = SSQ_NA, |
| 2871 | }, |
| 2872 | .sp_cmd_addr = { |
| 2873 | .address = 1024, |
| 2874 | .rowbits = 6, |
| 2875 | .bank = 0, |
| 2876 | .rank = slotrank, |
| 2877 | }, |
| 2878 | .addr_update = { |
| 2879 | .addr_wrap = 18, |
| 2880 | }, |
| 2881 | }; |
| 2882 | iosav_write_ssq(channel, &ssq); |
| 2883 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2884 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2885 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2886 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2887 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2888 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2889 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2890 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2891 | |
| 2892 | if (r32 == 0) |
| 2893 | lanes_ok |= 1 << lane; |
| 2894 | } |
| 2895 | ctr++; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2896 | if (lanes_ok == ((1 << ctrl->lanes) - 1)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2897 | break; |
| 2898 | } |
| 2899 | |
| 2900 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2901 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2902 | return lanes_ok != ((1 << ctrl->lanes) - 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2903 | } |
| 2904 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2905 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2906 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2907 | unsigned int i, j; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2908 | unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; |
| 2909 | unsigned int step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2910 | |
| 2911 | if (patno) { |
| 2912 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2913 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2914 | for (i = 0; i < 32; i++) { |
| 2915 | for (j = 0; j < 16; j++) { |
| 2916 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2917 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2918 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2919 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2920 | |
| 2921 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2922 | } |
| 2923 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2924 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2925 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 2926 | for (j = 0; j < 16; j++) { |
| 2927 | const u32 val = pattern[i][j]; |
| 2928 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 2929 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2930 | } |
| 2931 | sfence(); |
| 2932 | } |
| 2933 | } |
| 2934 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2935 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2936 | { |
| 2937 | int channel, slotrank; |
| 2938 | |
| 2939 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2940 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2941 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2942 | /* Choose an existing rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2943 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2944 | |
| 2945 | /* DRAM command ZQCS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2946 | { |
| 2947 | const struct iosav_ssq ssq = { |
| 2948 | .sp_cmd_ctrl = { |
| 2949 | .command = IOSAV_ZQCS, |
| 2950 | }, |
| 2951 | .subseq_ctrl = { |
| 2952 | .cmd_executions = 1, |
| 2953 | .cmd_delay_gap = 4, |
| 2954 | .post_ssq_wait = 4, |
| 2955 | .data_direction = SSQ_NA, |
| 2956 | }, |
| 2957 | .sp_cmd_addr = { |
| 2958 | .address = 0, |
| 2959 | .rowbits = 6, |
| 2960 | .bank = 0, |
| 2961 | .rank = slotrank, |
| 2962 | }, |
| 2963 | .addr_update = { |
| 2964 | .addr_wrap = 31, |
| 2965 | }, |
| 2966 | }; |
| 2967 | iosav_write_ssq(channel, &ssq); |
| 2968 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2969 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2970 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 2971 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2972 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2973 | wait_for_iosav(channel); |
| 2974 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2975 | } |
| 2976 | |
| 2977 | /* refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2978 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2979 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2980 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2981 | |
| 2982 | /* choose an existing rank. */ |
| 2983 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2984 | |
| 2985 | /* DRAM command ZQCS */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 2986 | { |
| 2987 | const struct iosav_ssq ssq = { |
| 2988 | .sp_cmd_ctrl = { |
| 2989 | .command = IOSAV_ZQCS, |
| 2990 | }, |
| 2991 | .subseq_ctrl = { |
| 2992 | .cmd_executions = 1, |
| 2993 | .cmd_delay_gap = 4, |
| 2994 | .post_ssq_wait = 4, |
| 2995 | .data_direction = SSQ_NA, |
| 2996 | }, |
| 2997 | .sp_cmd_addr = { |
| 2998 | .address = 0, |
| 2999 | .rowbits = 6, |
| 3000 | .bank = 0, |
| 3001 | .rank = slotrank, |
| 3002 | }, |
| 3003 | .addr_update = { |
| 3004 | .addr_wrap = 31, |
| 3005 | }, |
| 3006 | }; |
| 3007 | iosav_write_ssq(channel, &ssq); |
| 3008 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3009 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3010 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 3011 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3012 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3013 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3014 | } |
| 3015 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3016 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3017 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3018 | |
| 3019 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3020 | dram_mrscommands(ctrl); |
| 3021 | |
| 3022 | toggle_io_reset(); |
| 3023 | } |
| 3024 | |
| 3025 | #define MIN_C320C_LEN 13 |
| 3026 | |
| 3027 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 3028 | { |
| 3029 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 3030 | int slotrank; |
| 3031 | int c320c; |
| 3032 | int stat[NUM_SLOTRANKS][256]; |
| 3033 | int delta = 0; |
| 3034 | |
| 3035 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 3036 | |
| 3037 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3038 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3039 | } |
| 3040 | |
| 3041 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 3042 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3043 | MCHBAR32(TC_RAP_ch(channel)) = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3044 | (ctrl->tRRD << 0) |
| 3045 | | (ctrl->tRTP << 4) |
| 3046 | | (ctrl->tCKE << 8) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3047 | | (ctrl->tWTR << 12) |
| 3048 | | (ctrl->tFAW << 16) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3049 | | (ctrl->tWR << 24) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3050 | | (ctrl->cmd_stretch[channel] << 30); |
| 3051 | |
| 3052 | if (ctrl->cmd_stretch[channel] == 2) |
| 3053 | delta = 2; |
| 3054 | else if (ctrl->cmd_stretch[channel] == 0) |
| 3055 | delta = 4; |
| 3056 | |
| 3057 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3058 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3059 | } |
| 3060 | |
| 3061 | for (c320c = -127; c320c <= 127; c320c++) { |
| 3062 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3063 | ctrl->timings[channel][slotrank].pi_coding = c320c; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3064 | } |
| 3065 | program_timings(ctrl, channel); |
| 3066 | reprogram_320c(ctrl); |
| 3067 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3068 | stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3069 | } |
| 3070 | } |
| 3071 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3072 | struct run rn = get_longest_zero_run(stat[slotrank], 255); |
| 3073 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3074 | ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 3075 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 3076 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3077 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3078 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 3079 | FOR_ALL_POPULATED_RANKS { |
| 3080 | ctrl->timings[channel][slotrank] = |
| 3081 | saved_timings[channel][slotrank]; |
| 3082 | } |
| 3083 | return MAKE_ERR; |
| 3084 | } |
| 3085 | } |
| 3086 | |
| 3087 | return 0; |
| 3088 | } |
| 3089 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3090 | /* |
| 3091 | * Adjust CMD phase shift and try multiple command rates. |
| 3092 | * A command rate of 2T doubles the time needed for address and command decode. |
| 3093 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3094 | int command_training(ramctr_timing *ctrl) |
| 3095 | { |
| 3096 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3097 | |
| 3098 | FOR_ALL_POPULATED_CHANNELS { |
| 3099 | fill_pattern5(ctrl, channel, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3100 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3101 | } |
| 3102 | |
| 3103 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 3104 | int cmdrate, err; |
| 3105 | |
| 3106 | /* |
| 3107 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3108 | * Issue: |
| 3109 | * While c320c discovery seems to succeed raminit will fail in write training. |
| 3110 | * |
| 3111 | * Workaround: |
| 3112 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 3113 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 3114 | * |
| 3115 | * Single DIMM per channel: |
| 3116 | * Try command rate 1T and 2T |
| 3117 | */ |
| 3118 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 3119 | if (ctrl->tCMD) |
| 3120 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 3121 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 3122 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 3123 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 3124 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 3125 | |
| 3126 | if (!err) |
| 3127 | break; |
| 3128 | } |
| 3129 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3130 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 3131 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 3132 | return err; |
| 3133 | } |
| 3134 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3135 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3136 | } |
| 3137 | |
| 3138 | FOR_ALL_POPULATED_CHANNELS |
| 3139 | program_timings(ctrl, channel); |
| 3140 | |
| 3141 | reprogram_320c(ctrl); |
| 3142 | return 0; |
| 3143 | } |
| 3144 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3145 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3146 | { |
| 3147 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3148 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3149 | int lane; |
| 3150 | |
| 3151 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 3152 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3153 | ctrl->timings[channel][slotrank].lanes[lane].rising = edge; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3154 | ctrl->timings[channel][slotrank].lanes[lane].falling = edge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3155 | } |
| 3156 | program_timings(ctrl, channel); |
| 3157 | |
| 3158 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3159 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 3160 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3161 | } |
| 3162 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3163 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3164 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3165 | /* |
| 3166 | * DRAM command MRS |
| 3167 | * |
| 3168 | * Write MR3 MPR enable. |
| 3169 | * In this mode only RD and RDA are allowed, |
| 3170 | * and all reads return a predefined pattern. |
| 3171 | */ |
| 3172 | { |
| 3173 | const struct iosav_ssq ssq = { |
| 3174 | .sp_cmd_ctrl = { |
| 3175 | .command = IOSAV_MRS, |
| 3176 | .ranksel_ap = 1, |
| 3177 | }, |
| 3178 | .subseq_ctrl = { |
| 3179 | .cmd_executions = 1, |
| 3180 | .cmd_delay_gap = 3, |
| 3181 | .post_ssq_wait = ctrl->tMOD, |
| 3182 | .data_direction = SSQ_NA, |
| 3183 | }, |
| 3184 | .sp_cmd_addr = { |
| 3185 | .address = 4, |
| 3186 | .rowbits = 6, |
| 3187 | .bank = 3, |
| 3188 | .rank = slotrank, |
| 3189 | }, |
| 3190 | }; |
| 3191 | iosav_write_ssq(channel, &ssq); |
| 3192 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3193 | |
| 3194 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3195 | { |
| 3196 | const struct iosav_ssq ssq = { |
| 3197 | .sp_cmd_ctrl = { |
| 3198 | .command = IOSAV_RD, |
| 3199 | .ranksel_ap = 1, |
| 3200 | }, |
| 3201 | .subseq_ctrl = { |
| 3202 | .cmd_executions = 500, |
| 3203 | .cmd_delay_gap = 4, |
| 3204 | .post_ssq_wait = 4, |
| 3205 | .data_direction = SSQ_RD, |
| 3206 | }, |
| 3207 | .sp_cmd_addr = { |
| 3208 | .address = 0, |
| 3209 | .rowbits = 0, |
| 3210 | .bank = 0, |
| 3211 | .rank = slotrank, |
| 3212 | }, |
| 3213 | }; |
| 3214 | iosav_write_ssq(channel, &ssq); |
| 3215 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3216 | |
| 3217 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3218 | { |
| 3219 | const struct iosav_ssq ssq = { |
| 3220 | .sp_cmd_ctrl = { |
| 3221 | .command = IOSAV_RD, |
| 3222 | .ranksel_ap = 1, |
| 3223 | }, |
| 3224 | .subseq_ctrl = { |
| 3225 | .cmd_executions = 1, |
| 3226 | .cmd_delay_gap = 4, |
| 3227 | .post_ssq_wait = ctrl->CAS + 8, |
| 3228 | .data_direction = SSQ_NA, |
| 3229 | }, |
| 3230 | .sp_cmd_addr = { |
| 3231 | .address = 0, |
| 3232 | .rowbits = 6, |
| 3233 | .bank = 0, |
| 3234 | .rank = slotrank, |
| 3235 | }, |
| 3236 | }; |
| 3237 | iosav_write_ssq(channel, &ssq); |
| 3238 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3239 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3240 | /* |
| 3241 | * DRAM command MRS |
| 3242 | * |
| 3243 | * Write MR3 MPR disable. |
| 3244 | */ |
| 3245 | { |
| 3246 | const struct iosav_ssq ssq = { |
| 3247 | .sp_cmd_ctrl = { |
| 3248 | .command = IOSAV_MRS, |
| 3249 | .ranksel_ap = 1, |
| 3250 | }, |
| 3251 | .subseq_ctrl = { |
| 3252 | .cmd_executions = 1, |
| 3253 | .cmd_delay_gap = 3, |
| 3254 | .post_ssq_wait = ctrl->tMOD, |
| 3255 | .data_direction = SSQ_NA, |
| 3256 | }, |
| 3257 | .sp_cmd_addr = { |
| 3258 | .address = 0, |
| 3259 | .rowbits = 6, |
| 3260 | .bank = 3, |
| 3261 | .rank = slotrank, |
| 3262 | }, |
| 3263 | }; |
| 3264 | iosav_write_ssq(channel, &ssq); |
| 3265 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3266 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3267 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 3268 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3269 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3270 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3271 | |
| 3272 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3273 | stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3274 | } |
| 3275 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3276 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3277 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3278 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3279 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3280 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3281 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3282 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, |
| 3283 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3284 | return MAKE_ERR; |
| 3285 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3286 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3287 | } |
| 3288 | return 0; |
| 3289 | } |
| 3290 | |
| 3291 | int discover_edges(ramctr_timing *ctrl) |
| 3292 | { |
| 3293 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 3294 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 3295 | int channel, slotrank, lane; |
| 3296 | int err; |
| 3297 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3298 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3299 | |
| 3300 | toggle_io_reset(); |
| 3301 | |
| 3302 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3303 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3304 | } |
| 3305 | |
| 3306 | FOR_ALL_POPULATED_CHANNELS { |
| 3307 | fill_pattern0(ctrl, channel, 0, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3308 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3309 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3310 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3311 | } |
| 3312 | |
| 3313 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3314 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 3315 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3316 | } |
| 3317 | |
| 3318 | program_timings(ctrl, channel); |
| 3319 | |
| 3320 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3321 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3322 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3323 | /* |
| 3324 | * DRAM command MRS |
| 3325 | * |
| 3326 | * Write MR3 MPR enable. |
| 3327 | * In this mode only RD and RDA are allowed, |
| 3328 | * and all reads return a predefined pattern. |
| 3329 | */ |
| 3330 | { |
| 3331 | const struct iosav_ssq ssq = { |
| 3332 | .sp_cmd_ctrl = { |
| 3333 | .command = IOSAV_MRS, |
| 3334 | .ranksel_ap = 1, |
| 3335 | }, |
| 3336 | .subseq_ctrl = { |
| 3337 | .cmd_executions = 1, |
| 3338 | .cmd_delay_gap = 3, |
| 3339 | .post_ssq_wait = ctrl->tMOD, |
| 3340 | .data_direction = SSQ_NA, |
| 3341 | }, |
| 3342 | .sp_cmd_addr = { |
| 3343 | .address = 4, |
| 3344 | .rowbits = 6, |
| 3345 | .bank = 3, |
| 3346 | .rank = slotrank, |
| 3347 | }, |
| 3348 | }; |
| 3349 | iosav_write_ssq(channel, &ssq); |
| 3350 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3351 | |
| 3352 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3353 | { |
| 3354 | const struct iosav_ssq ssq = { |
| 3355 | .sp_cmd_ctrl = { |
| 3356 | .command = IOSAV_RD, |
| 3357 | .ranksel_ap = 1, |
| 3358 | }, |
| 3359 | .subseq_ctrl = { |
| 3360 | .cmd_executions = 3, |
| 3361 | .cmd_delay_gap = 4, |
| 3362 | .post_ssq_wait = 4, |
| 3363 | .data_direction = SSQ_RD, |
| 3364 | }, |
| 3365 | .sp_cmd_addr = { |
| 3366 | .address = 0, |
| 3367 | .rowbits = 0, |
| 3368 | .bank = 0, |
| 3369 | .rank = slotrank, |
| 3370 | }, |
| 3371 | }; |
| 3372 | iosav_write_ssq(channel, &ssq); |
| 3373 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3374 | |
| 3375 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3376 | { |
| 3377 | const struct iosav_ssq ssq = { |
| 3378 | .sp_cmd_ctrl = { |
| 3379 | .command = IOSAV_RD, |
| 3380 | .ranksel_ap = 1, |
| 3381 | }, |
| 3382 | .subseq_ctrl = { |
| 3383 | .cmd_executions = 1, |
| 3384 | .cmd_delay_gap = 4, |
| 3385 | .post_ssq_wait = ctrl->CAS + 8, |
| 3386 | .data_direction = SSQ_NA, |
| 3387 | }, |
| 3388 | .sp_cmd_addr = { |
| 3389 | .address = 0, |
| 3390 | .rowbits = 6, |
| 3391 | .bank = 0, |
| 3392 | .rank = slotrank, |
| 3393 | }, |
| 3394 | }; |
| 3395 | iosav_write_ssq(channel, &ssq); |
| 3396 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3397 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3398 | /* |
| 3399 | * DRAM command MRS |
| 3400 | * |
| 3401 | * Write MR3 MPR disable. |
| 3402 | */ |
| 3403 | { |
| 3404 | const struct iosav_ssq ssq = { |
| 3405 | .sp_cmd_ctrl = { |
| 3406 | .command = IOSAV_MRS, |
| 3407 | .ranksel_ap = 1, |
| 3408 | }, |
| 3409 | .subseq_ctrl = { |
| 3410 | .cmd_executions = 1, |
| 3411 | .cmd_delay_gap = 3, |
| 3412 | .post_ssq_wait = ctrl->tMOD, |
| 3413 | .data_direction = SSQ_NA, |
| 3414 | }, |
| 3415 | .sp_cmd_addr = { |
| 3416 | .address = 0, |
| 3417 | .rowbits = 6, |
| 3418 | .bank = 3, |
| 3419 | .rank = slotrank, |
| 3420 | }, |
| 3421 | }; |
| 3422 | iosav_write_ssq(channel, &ssq); |
| 3423 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3424 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3425 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 3426 | iosav_run_once(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3427 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3428 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3429 | } |
| 3430 | |
| 3431 | /* XXX: check any measured value ? */ |
| 3432 | |
| 3433 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3434 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3435 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3436 | } |
| 3437 | |
| 3438 | program_timings(ctrl, channel); |
| 3439 | |
| 3440 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3441 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3442 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3443 | /* |
| 3444 | * DRAM command MRS |
| 3445 | * |
| 3446 | * Write MR3 MPR enable. |
| 3447 | * In this mode only RD and RDA are allowed, |
| 3448 | * and all reads return a predefined pattern. |
| 3449 | */ |
| 3450 | { |
| 3451 | const struct iosav_ssq ssq = { |
| 3452 | .sp_cmd_ctrl = { |
| 3453 | .command = IOSAV_MRS, |
| 3454 | .ranksel_ap = 1, |
| 3455 | }, |
| 3456 | .subseq_ctrl = { |
| 3457 | .cmd_executions = 1, |
| 3458 | .cmd_delay_gap = 3, |
| 3459 | .post_ssq_wait = ctrl->tMOD, |
| 3460 | .data_direction = SSQ_NA, |
| 3461 | }, |
| 3462 | .sp_cmd_addr = { |
| 3463 | .address = 4, |
| 3464 | .rowbits = 6, |
| 3465 | .bank = 3, |
| 3466 | .rank = slotrank, |
| 3467 | }, |
| 3468 | }; |
| 3469 | iosav_write_ssq(channel, &ssq); |
| 3470 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3471 | |
| 3472 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3473 | { |
| 3474 | const struct iosav_ssq ssq = { |
| 3475 | .sp_cmd_ctrl = { |
| 3476 | .command = IOSAV_RD, |
| 3477 | .ranksel_ap = 1, |
| 3478 | }, |
| 3479 | .subseq_ctrl = { |
| 3480 | .cmd_executions = 3, |
| 3481 | .cmd_delay_gap = 4, |
| 3482 | .post_ssq_wait = 4, |
| 3483 | .data_direction = SSQ_RD, |
| 3484 | }, |
| 3485 | .sp_cmd_addr = { |
| 3486 | .address = 0, |
| 3487 | .rowbits = 0, |
| 3488 | .bank = 0, |
| 3489 | .rank = slotrank, |
| 3490 | }, |
| 3491 | }; |
| 3492 | iosav_write_ssq(channel, &ssq); |
| 3493 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3494 | |
| 3495 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3496 | { |
| 3497 | const struct iosav_ssq ssq = { |
| 3498 | .sp_cmd_ctrl = { |
| 3499 | .command = IOSAV_RD, |
| 3500 | .ranksel_ap = 1, |
| 3501 | }, |
| 3502 | .subseq_ctrl = { |
| 3503 | .cmd_executions = 1, |
| 3504 | .cmd_delay_gap = 4, |
| 3505 | .post_ssq_wait = ctrl->CAS + 8, |
| 3506 | .data_direction = SSQ_NA, |
| 3507 | }, |
| 3508 | .sp_cmd_addr = { |
| 3509 | .address = 0, |
| 3510 | .rowbits = 6, |
| 3511 | .bank = 0, |
| 3512 | .rank = slotrank, |
| 3513 | }, |
| 3514 | }; |
| 3515 | iosav_write_ssq(channel, &ssq); |
| 3516 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3517 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3518 | /* |
| 3519 | * DRAM command MRS |
| 3520 | * |
| 3521 | * Write MR3 MPR disable. |
| 3522 | */ |
| 3523 | { |
| 3524 | const struct iosav_ssq ssq = { |
| 3525 | .sp_cmd_ctrl = { |
| 3526 | .command = IOSAV_MRS, |
| 3527 | .ranksel_ap = 1, |
| 3528 | }, |
| 3529 | .subseq_ctrl = { |
| 3530 | .cmd_executions = 1, |
| 3531 | .cmd_delay_gap = 3, |
| 3532 | .post_ssq_wait = ctrl->tMOD, |
| 3533 | .data_direction = SSQ_NA, |
| 3534 | }, |
| 3535 | .sp_cmd_addr = { |
| 3536 | .address = 0, |
| 3537 | .rowbits = 6, |
| 3538 | .bank = 3, |
| 3539 | .rank = slotrank, |
| 3540 | }, |
| 3541 | }; |
| 3542 | iosav_write_ssq(channel, &ssq); |
| 3543 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3544 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3545 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 3546 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3547 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3548 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3549 | } |
| 3550 | |
| 3551 | /* XXX: check any measured value ? */ |
| 3552 | |
| 3553 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3554 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3555 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3556 | } |
| 3557 | |
| 3558 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3559 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3560 | } |
| 3561 | |
Angel Pons | 0c3936e | 2020-03-22 12:49:27 +0100 | [diff] [blame] | 3562 | /* |
| 3563 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 3564 | * also use a single loop. It would seem that it is a debugging configuration. |
| 3565 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3566 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 3567 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3568 | |
| 3569 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 3570 | err = discover_edges_real(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 3571 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3572 | if (err) |
| 3573 | return err; |
| 3574 | } |
| 3575 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3576 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 3577 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3578 | |
| 3579 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 3580 | err = discover_edges_real(ctrl, channel, slotrank, |
| 3581 | rising_edges[channel][slotrank]); |
| 3582 | if (err) |
| 3583 | return err; |
| 3584 | } |
| 3585 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3586 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3587 | |
| 3588 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 3589 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 3590 | falling_edges[channel][slotrank][lane]; |
| 3591 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 3592 | rising_edges[channel][slotrank][lane]; |
| 3593 | } |
| 3594 | |
| 3595 | FOR_ALL_POPULATED_CHANNELS { |
| 3596 | program_timings(ctrl, channel); |
| 3597 | } |
| 3598 | |
| 3599 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3600 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3601 | } |
| 3602 | return 0; |
| 3603 | } |
| 3604 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3605 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3606 | { |
| 3607 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3608 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
| 3609 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3610 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 3611 | int lane, i; |
| 3612 | int lower[NUM_LANES]; |
| 3613 | int upper[NUM_LANES]; |
| 3614 | int pat; |
| 3615 | |
| 3616 | FOR_ALL_LANES { |
| 3617 | lower[lane] = 0; |
| 3618 | upper[lane] = MAX_EDGE_TIMING; |
| 3619 | } |
| 3620 | |
| 3621 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3622 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3623 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
| 3624 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3625 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 3626 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3627 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3628 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3629 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3630 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 3631 | FOR_ALL_LANES { |
| 3632 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 3633 | rising = edge; |
| 3634 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 3635 | falling = edge; |
| 3636 | } |
| 3637 | program_timings(ctrl, channel); |
| 3638 | |
| 3639 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3640 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 3641 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3642 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3643 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3644 | |
| 3645 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3646 | { |
| 3647 | const struct iosav_ssq ssq = { |
| 3648 | .sp_cmd_ctrl = { |
| 3649 | .command = IOSAV_ACT, |
| 3650 | .ranksel_ap = 1, |
| 3651 | }, |
| 3652 | .subseq_ctrl = { |
| 3653 | .cmd_executions = 4, |
| 3654 | .cmd_delay_gap = MAX(ctrl->tRRD, |
| 3655 | (ctrl->tFAW >> 2) + 1), |
| 3656 | .post_ssq_wait = ctrl->tRCD, |
| 3657 | .data_direction = SSQ_NA, |
| 3658 | }, |
| 3659 | .sp_cmd_addr = { |
| 3660 | .address = 0, |
| 3661 | .rowbits = 6, |
| 3662 | .bank = 0, |
| 3663 | .rank = slotrank, |
| 3664 | }, |
| 3665 | .addr_update = { |
| 3666 | .addr_wrap = 18, |
| 3667 | }, |
| 3668 | }; |
| 3669 | iosav_write_ssq(channel, &ssq); |
| 3670 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3671 | |
| 3672 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3673 | { |
| 3674 | const struct iosav_ssq ssq = { |
| 3675 | .sp_cmd_ctrl = { |
| 3676 | .command = IOSAV_WR, |
| 3677 | .ranksel_ap = 1, |
| 3678 | }, |
| 3679 | .subseq_ctrl = { |
| 3680 | .cmd_executions = 32, |
| 3681 | .cmd_delay_gap = 20, |
| 3682 | .post_ssq_wait = ctrl->tWTR + |
| 3683 | ctrl->CWL + 8, |
| 3684 | .data_direction = SSQ_WR, |
| 3685 | }, |
| 3686 | .sp_cmd_addr = { |
| 3687 | .address = 0, |
| 3688 | .rowbits = 0, |
| 3689 | .bank = 0, |
| 3690 | .rank = slotrank, |
| 3691 | }, |
| 3692 | .addr_update = { |
| 3693 | .inc_addr_8 = 1, |
| 3694 | .addr_wrap = 18, |
| 3695 | }, |
| 3696 | }; |
| 3697 | iosav_write_ssq(channel, &ssq); |
| 3698 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3699 | |
| 3700 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3701 | { |
| 3702 | const struct iosav_ssq ssq = { |
| 3703 | .sp_cmd_ctrl = { |
| 3704 | .command = IOSAV_RD, |
| 3705 | .ranksel_ap = 1, |
| 3706 | }, |
| 3707 | .subseq_ctrl = { |
| 3708 | .cmd_executions = 32, |
| 3709 | .cmd_delay_gap = 20, |
| 3710 | .post_ssq_wait = MAX(ctrl->tRTP, 8), |
| 3711 | .data_direction = SSQ_RD, |
| 3712 | }, |
| 3713 | .sp_cmd_addr = { |
| 3714 | .address = 0, |
| 3715 | .rowbits = 0, |
| 3716 | .bank = 0, |
| 3717 | .rank = slotrank, |
| 3718 | }, |
| 3719 | .addr_update = { |
| 3720 | .inc_addr_8 = 1, |
| 3721 | .addr_wrap = 18, |
| 3722 | }, |
| 3723 | }; |
| 3724 | iosav_write_ssq(channel, &ssq); |
| 3725 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3726 | |
| 3727 | /* DRAM command PRE */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3728 | { |
| 3729 | const struct iosav_ssq ssq = { |
| 3730 | .sp_cmd_ctrl = { |
| 3731 | .command = IOSAV_PRE, |
| 3732 | .ranksel_ap = 1, |
| 3733 | }, |
| 3734 | .subseq_ctrl = { |
| 3735 | .cmd_executions = 1, |
| 3736 | .cmd_delay_gap = 3, |
| 3737 | .post_ssq_wait = ctrl->tRP, |
| 3738 | .data_direction = SSQ_NA, |
| 3739 | }, |
| 3740 | .sp_cmd_addr = { |
| 3741 | .address = 1024, |
| 3742 | .rowbits = 6, |
| 3743 | .bank = 0, |
| 3744 | .rank = slotrank, |
| 3745 | }, |
| 3746 | }; |
| 3747 | iosav_write_ssq(channel, &ssq); |
| 3748 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3749 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3750 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 3751 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3752 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3753 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3754 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3755 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3756 | } |
| 3757 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3758 | /* FIXME: This register only exists on Ivy Bridge */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 3759 | raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3760 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3761 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3762 | FOR_ALL_LANES { |
| 3763 | struct run rn; |
| 3764 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3765 | stats[edge] = !!(raw_stats[edge] & (1 << lane)); |
| 3766 | |
| 3767 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 3768 | |
| 3769 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " |
| 3770 | "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, |
| 3771 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3772 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3773 | |
| 3774 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 3775 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 3776 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3777 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 3778 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3779 | printk(BIOS_EMERG, "edge write discovery failed: " |
| 3780 | "%d, %d, %d\n", channel, slotrank, lane); |
| 3781 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3782 | return MAKE_ERR; |
| 3783 | } |
| 3784 | } |
| 3785 | } |
| 3786 | } |
| 3787 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3788 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3789 | printram("CPA\n"); |
| 3790 | return 0; |
| 3791 | } |
| 3792 | |
| 3793 | int discover_edges_write(ramctr_timing *ctrl) |
| 3794 | { |
| 3795 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3796 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 3797 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3798 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3799 | /* |
| 3800 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 3801 | * also use a single loop. It would seem that it is a debugging configuration. |
| 3802 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3803 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 3804 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3805 | |
| 3806 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 3807 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3808 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3809 | if (err) |
| 3810 | return err; |
| 3811 | } |
| 3812 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3813 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 3814 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3815 | |
| 3816 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 3817 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3818 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3819 | if (err) |
| 3820 | return err; |
| 3821 | } |
| 3822 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3823 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3824 | |
| 3825 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 3826 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3827 | falling_edges[channel][slotrank][lane]; |
| 3828 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3829 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3830 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3831 | } |
| 3832 | |
| 3833 | FOR_ALL_POPULATED_CHANNELS |
| 3834 | program_timings(ctrl, channel); |
| 3835 | |
| 3836 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3837 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3838 | } |
| 3839 | return 0; |
| 3840 | } |
| 3841 | |
| 3842 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 3843 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3844 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3845 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3846 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3847 | { |
| 3848 | const struct iosav_ssq ssq = { |
| 3849 | .sp_cmd_ctrl = { |
| 3850 | .command = IOSAV_ACT, |
| 3851 | .ranksel_ap = 1, |
| 3852 | }, |
| 3853 | .subseq_ctrl = { |
| 3854 | .cmd_executions = 4, |
| 3855 | .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), |
| 3856 | .post_ssq_wait = ctrl->tRCD, |
| 3857 | .data_direction = SSQ_NA, |
| 3858 | }, |
| 3859 | .sp_cmd_addr = { |
| 3860 | .address = 0, |
| 3861 | .rowbits = 6, |
| 3862 | .bank = 0, |
| 3863 | .rank = slotrank, |
| 3864 | }, |
| 3865 | .addr_update = { |
| 3866 | .inc_bank = 1, |
| 3867 | .addr_wrap = 18, |
| 3868 | }, |
| 3869 | }; |
| 3870 | iosav_write_ssq(channel, &ssq); |
| 3871 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3872 | |
| 3873 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3874 | { |
| 3875 | const struct iosav_ssq ssq = { |
| 3876 | .sp_cmd_ctrl = { |
| 3877 | .command = IOSAV_WR, |
| 3878 | .ranksel_ap = 1, |
| 3879 | }, |
| 3880 | .subseq_ctrl = { |
| 3881 | .cmd_executions = 480, |
| 3882 | .cmd_delay_gap = 4, |
| 3883 | .post_ssq_wait = ctrl->tWTR + ctrl->CWL + 8, |
| 3884 | .data_direction = SSQ_WR, |
| 3885 | }, |
| 3886 | .sp_cmd_addr = { |
| 3887 | .address = 0, |
| 3888 | .rowbits = 0, |
| 3889 | .bank = 0, |
| 3890 | .rank = slotrank, |
| 3891 | }, |
| 3892 | .addr_update = { |
| 3893 | .inc_addr_8 = 1, |
| 3894 | .addr_wrap = 18, |
| 3895 | }, |
| 3896 | }; |
| 3897 | iosav_write_ssq(channel, &ssq); |
| 3898 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3899 | |
| 3900 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3901 | { |
| 3902 | const struct iosav_ssq ssq = { |
| 3903 | .sp_cmd_ctrl = { |
| 3904 | .command = IOSAV_RD, |
| 3905 | .ranksel_ap = 1, |
| 3906 | }, |
| 3907 | .subseq_ctrl = { |
| 3908 | .cmd_executions = 480, |
| 3909 | .cmd_delay_gap = 4, |
| 3910 | .post_ssq_wait = MAX(ctrl->tRTP, 8), |
| 3911 | .data_direction = SSQ_RD, |
| 3912 | }, |
| 3913 | .sp_cmd_addr = { |
| 3914 | .address = 0, |
| 3915 | .rowbits = 0, |
| 3916 | .bank = 0, |
| 3917 | .rank = slotrank, |
| 3918 | }, |
| 3919 | .addr_update = { |
| 3920 | .inc_addr_8 = 1, |
| 3921 | .addr_wrap = 18, |
| 3922 | }, |
| 3923 | }; |
| 3924 | iosav_write_ssq(channel, &ssq); |
| 3925 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3926 | |
| 3927 | /* DRAM command PRE */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 3928 | { |
| 3929 | const struct iosav_ssq ssq = { |
| 3930 | .sp_cmd_ctrl = { |
| 3931 | .command = IOSAV_PRE, |
| 3932 | .ranksel_ap = 1, |
| 3933 | }, |
| 3934 | .subseq_ctrl = { |
| 3935 | .cmd_executions = 1, |
| 3936 | .cmd_delay_gap = 4, |
| 3937 | .post_ssq_wait = ctrl->tRP, |
| 3938 | .data_direction = SSQ_NA, |
| 3939 | }, |
| 3940 | .sp_cmd_addr = { |
| 3941 | .address = 1024, |
| 3942 | .rowbits = 6, |
| 3943 | .bank = 0, |
| 3944 | .rank = slotrank, |
| 3945 | }, |
| 3946 | }; |
| 3947 | iosav_write_ssq(channel, &ssq); |
| 3948 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3949 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3950 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 3951 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 3952 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3953 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3954 | } |
| 3955 | |
| 3956 | int discover_timC_write(ramctr_timing *ctrl) |
| 3957 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3958 | const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3959 | int i, pat; |
| 3960 | |
| 3961 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 3962 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 3963 | int channel, slotrank, lane; |
| 3964 | |
| 3965 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 3966 | lower[channel][slotrank][lane] = 0; |
| 3967 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 3968 | } |
| 3969 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3970 | /* |
| 3971 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 3972 | * FIXME: This must only be done on Ivy Bridge. |
| 3973 | */ |
| 3974 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3975 | printram("discover timC write:\n"); |
| 3976 | |
| 3977 | for (i = 0; i < 3; i++) |
| 3978 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3979 | |
| 3980 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
| 3981 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), |
| 3982 | ~0x3f000000, rege3c_b24[i] << 24); |
| 3983 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3984 | udelay(2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3985 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3986 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 3987 | FOR_ALL_POPULATED_RANKS { |
| 3988 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3989 | u32 raw_stats[MAX_TIMC + 1]; |
| 3990 | int stats[MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3991 | |
| 3992 | /* Make sure rn.start < rn.end */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3993 | stats[MAX_TIMC] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3994 | |
| 3995 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3996 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
| 3997 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3998 | for (timC = 0; timC < MAX_TIMC; timC++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3999 | FOR_ALL_LANES { |
| 4000 | ctrl->timings[channel][slotrank] |
| 4001 | .lanes[lane].timC = timC; |
| 4002 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4003 | program_timings(ctrl, channel); |
| 4004 | |
| 4005 | test_timC_write (ctrl, channel, slotrank); |
| 4006 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4007 | /* FIXME: Another IVB-only register! */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 4008 | raw_stats[timC] = MCHBAR32( |
| 4009 | IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4010 | } |
| 4011 | FOR_ALL_LANES { |
| 4012 | struct run rn; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4013 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 4014 | stats[timC] = !!(raw_stats[timC] |
| 4015 | & (1 << lane)); |
| 4016 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4017 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4018 | rn = get_longest_zero_run(stats, MAX_TIMC + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4019 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4020 | printk(BIOS_EMERG, |
| 4021 | "timC write discovery failed: " |
| 4022 | "%d, %d, %d\n", channel, |
| 4023 | slotrank, lane); |
| 4024 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4025 | return MAKE_ERR; |
| 4026 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4027 | printram("timC: %d, %d, %d: " |
| 4028 | "0x%02x-0x%02x-0x%02x, " |
| 4029 | "0x%02x-0x%02x\n", channel, slotrank, |
| 4030 | i, rn.start, rn.middle, rn.end, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4031 | rn.start + ctrl->timC_offset[i], |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4032 | rn.end - ctrl->timC_offset[i]); |
| 4033 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4034 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 4035 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4036 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4037 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4038 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 4039 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4040 | upper[channel][slotrank][lane]); |
| 4041 | |
| 4042 | } |
| 4043 | } |
| 4044 | } |
| 4045 | } |
| 4046 | |
| 4047 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4048 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4049 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4050 | udelay(2); |
| 4051 | } |
| 4052 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4053 | /* |
| 4054 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 4055 | * FIXME: This must only be done on Ivy Bridge. |
| 4056 | */ |
| 4057 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4058 | |
| 4059 | printram("CPB\n"); |
| 4060 | |
| 4061 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4062 | printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4063 | (lower[channel][slotrank][lane] + |
| 4064 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4065 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4066 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 4067 | (lower[channel][slotrank][lane] + |
| 4068 | upper[channel][slotrank][lane]) / 2; |
| 4069 | } |
| 4070 | FOR_ALL_POPULATED_CHANNELS { |
| 4071 | program_timings(ctrl, channel); |
| 4072 | } |
| 4073 | return 0; |
| 4074 | } |
| 4075 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4076 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4077 | { |
| 4078 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 4079 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4080 | |
| 4081 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 4082 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 4083 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4084 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 4085 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 4086 | printram("normalize %d, %d, %d: mat %d\n", |
| 4087 | channel, slotrank, lane, mat); |
| 4088 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 4089 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 4090 | printram("normalize %d, %d, %d: delta %d\n", |
| 4091 | channel, slotrank, lane, delta); |
| 4092 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4093 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 4094 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4095 | } |
| 4096 | |
| 4097 | FOR_ALL_POPULATED_CHANNELS { |
| 4098 | program_timings(ctrl, channel); |
| 4099 | } |
| 4100 | } |
| 4101 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4102 | void write_controller_mr(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4103 | { |
| 4104 | int channel, slotrank; |
| 4105 | |
| 4106 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 4107 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 4108 | make_mr0(ctrl, slotrank); |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 4109 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 4110 | make_mr1(ctrl, slotrank, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4111 | } |
| 4112 | } |
| 4113 | |
| 4114 | int channel_test(ramctr_timing *ctrl) |
| 4115 | { |
| 4116 | int channel, slotrank, lane; |
| 4117 | |
| 4118 | slotrank = 0; |
| 4119 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4120 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 4121 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4122 | return MAKE_ERR; |
| 4123 | } |
| 4124 | FOR_ALL_POPULATED_CHANNELS { |
| 4125 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
| 4126 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4127 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4128 | } |
| 4129 | |
| 4130 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 4131 | FOR_ALL_CHANNELS |
| 4132 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 4133 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4134 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 4135 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4136 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4137 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 4138 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4139 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4140 | { |
| 4141 | const struct iosav_ssq ssq = { |
| 4142 | .sp_cmd_ctrl = { |
| 4143 | .command = IOSAV_ACT, |
| 4144 | .ranksel_ap = 1, |
| 4145 | }, |
| 4146 | .subseq_ctrl = { |
| 4147 | .cmd_executions = 4, |
| 4148 | .cmd_delay_gap = 8, |
| 4149 | .post_ssq_wait = 40, |
| 4150 | .data_direction = SSQ_NA, |
| 4151 | }, |
| 4152 | .sp_cmd_addr = { |
| 4153 | .address = 0, |
| 4154 | .rowbits = 6, |
| 4155 | .bank = 0, |
| 4156 | .rank = slotrank, |
| 4157 | }, |
| 4158 | .addr_update = { |
| 4159 | .inc_bank = 1, |
| 4160 | .addr_wrap = 18, |
| 4161 | }, |
| 4162 | }; |
| 4163 | iosav_write_ssq(channel, &ssq); |
| 4164 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 4165 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4166 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4167 | { |
| 4168 | const struct iosav_ssq ssq = { |
| 4169 | .sp_cmd_ctrl = { |
| 4170 | .command = IOSAV_WR, |
| 4171 | .ranksel_ap = 1, |
| 4172 | }, |
| 4173 | .subseq_ctrl = { |
| 4174 | .cmd_executions = 100, |
| 4175 | .cmd_delay_gap = 4, |
| 4176 | .post_ssq_wait = 40, |
| 4177 | .data_direction = SSQ_WR, |
| 4178 | }, |
| 4179 | .sp_cmd_addr = { |
| 4180 | .address = 0, |
| 4181 | .rowbits = 0, |
| 4182 | .bank = 0, |
| 4183 | .rank = slotrank, |
| 4184 | }, |
| 4185 | .addr_update = { |
| 4186 | .inc_addr_8 = 1, |
| 4187 | .addr_wrap = 18, |
| 4188 | }, |
| 4189 | }; |
| 4190 | iosav_write_ssq(channel, &ssq); |
| 4191 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 4192 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4193 | /* DRAM command RD */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4194 | { |
| 4195 | const struct iosav_ssq ssq = { |
| 4196 | .sp_cmd_ctrl = { |
| 4197 | .command = IOSAV_RD, |
| 4198 | .ranksel_ap = 1, |
| 4199 | }, |
| 4200 | .subseq_ctrl = { |
| 4201 | .cmd_executions = 100, |
| 4202 | .cmd_delay_gap = 4, |
| 4203 | .post_ssq_wait = 40, |
| 4204 | .data_direction = SSQ_RD, |
| 4205 | }, |
| 4206 | .sp_cmd_addr = { |
| 4207 | .address = 0, |
| 4208 | .rowbits = 0, |
| 4209 | .bank = 0, |
| 4210 | .rank = slotrank, |
| 4211 | }, |
| 4212 | .addr_update = { |
| 4213 | .inc_addr_8 = 1, |
| 4214 | .addr_wrap = 18, |
| 4215 | }, |
| 4216 | }; |
| 4217 | iosav_write_ssq(channel, &ssq); |
| 4218 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 4219 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4220 | /* DRAM command PRE */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4221 | { |
| 4222 | const struct iosav_ssq ssq = { |
| 4223 | .sp_cmd_ctrl = { |
| 4224 | .command = IOSAV_PRE, |
| 4225 | .ranksel_ap = 1, |
| 4226 | }, |
| 4227 | .subseq_ctrl = { |
| 4228 | .cmd_executions = 1, |
| 4229 | .cmd_delay_gap = 3, |
| 4230 | .post_ssq_wait = 40, |
| 4231 | .data_direction = SSQ_NA, |
| 4232 | }, |
| 4233 | .sp_cmd_addr = { |
| 4234 | .address = 1024, |
| 4235 | .rowbits = 6, |
| 4236 | .bank = 0, |
| 4237 | .rank = slotrank, |
| 4238 | }, |
| 4239 | .addr_update = { |
| 4240 | .addr_wrap = 18, |
| 4241 | }, |
| 4242 | }; |
| 4243 | iosav_write_ssq(channel, &ssq); |
| 4244 | } |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 4245 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4246 | /* Execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 4247 | iosav_run_once(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 4248 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4249 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4250 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4251 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4252 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 4253 | channel, slotrank, lane); |
| 4254 | return MAKE_ERR; |
| 4255 | } |
| 4256 | } |
| 4257 | return 0; |
| 4258 | } |
| 4259 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 4260 | void channel_scrub(ramctr_timing *ctrl) |
| 4261 | { |
| 4262 | int channel, slotrank, row, rowsize; |
| 4263 | |
| 4264 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 4265 | rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; |
| 4266 | for (row = 0; row < rowsize; row += 16) { |
| 4267 | |
| 4268 | wait_for_iosav(channel); |
| 4269 | |
| 4270 | /* DRAM command ACT */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4271 | { |
| 4272 | const struct iosav_ssq ssq = { |
| 4273 | .sp_cmd_ctrl = { |
| 4274 | .command = IOSAV_ACT, |
| 4275 | .ranksel_ap = 1, |
| 4276 | }, |
| 4277 | .subseq_ctrl = { |
| 4278 | .cmd_executions = 1, |
| 4279 | .cmd_delay_gap = MAX((ctrl->tFAW >> 2) + 1, |
| 4280 | ctrl->tRRD), |
| 4281 | .post_ssq_wait = ctrl->tRCD, |
| 4282 | .data_direction = SSQ_NA, |
| 4283 | }, |
| 4284 | .sp_cmd_addr = { |
| 4285 | .address = row, |
| 4286 | .rowbits = 6, |
| 4287 | .bank = 0, |
| 4288 | .rank = slotrank, |
| 4289 | }, |
| 4290 | .addr_update = { |
| 4291 | .inc_addr_1 = 1, |
| 4292 | .addr_wrap = 18, |
| 4293 | }, |
| 4294 | }; |
| 4295 | iosav_write_ssq(channel, &ssq); |
| 4296 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 4297 | |
| 4298 | /* DRAM command WR */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4299 | { |
| 4300 | const struct iosav_ssq ssq = { |
| 4301 | .sp_cmd_ctrl = { |
| 4302 | .command = IOSAV_WR, |
| 4303 | .ranksel_ap = 1, |
| 4304 | }, |
| 4305 | .subseq_ctrl = { |
| 4306 | .cmd_executions = 129, |
| 4307 | .cmd_delay_gap = 4, |
| 4308 | .post_ssq_wait = 40, |
| 4309 | .data_direction = SSQ_WR, |
| 4310 | }, |
| 4311 | .sp_cmd_addr = { |
| 4312 | .address = row, |
| 4313 | .rowbits = 0, |
| 4314 | .bank = 0, |
| 4315 | .rank = slotrank, |
| 4316 | }, |
| 4317 | .addr_update = { |
| 4318 | .inc_addr_8 = 1, |
| 4319 | .addr_wrap = 18, |
| 4320 | }, |
| 4321 | }; |
| 4322 | iosav_write_ssq(channel, &ssq); |
| 4323 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 4324 | |
| 4325 | /* DRAM command PRE */ |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 4326 | { |
| 4327 | const struct iosav_ssq ssq = { |
| 4328 | .sp_cmd_ctrl = { |
| 4329 | .command = IOSAV_PRE, |
| 4330 | .ranksel_ap = 1, |
| 4331 | }, |
| 4332 | .subseq_ctrl = { |
| 4333 | .cmd_executions = 1, |
| 4334 | .cmd_delay_gap = 3, |
| 4335 | .post_ssq_wait = 40, |
| 4336 | .data_direction = SSQ_NA, |
| 4337 | }, |
| 4338 | .sp_cmd_addr = { |
| 4339 | .address = 1024, |
| 4340 | .rowbits = 6, |
| 4341 | .bank = 0, |
| 4342 | .rank = slotrank, |
| 4343 | }, |
| 4344 | .addr_update = { |
| 4345 | .addr_wrap = 18, |
| 4346 | }, |
| 4347 | }; |
| 4348 | iosav_write_ssq(channel, &ssq); |
| 4349 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 4350 | |
| 4351 | /* execute command queue */ |
Angel Pons | 38d901e | 2020-05-02 23:50:43 +0200 | [diff] [blame] | 4352 | iosav_run_once(channel); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 4353 | |
| 4354 | wait_for_iosav(channel); |
| 4355 | } |
| 4356 | } |
| 4357 | } |
| 4358 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4359 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4360 | { |
| 4361 | int channel; |
| 4362 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4363 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4364 | static u32 seeds[NUM_CHANNELS][3] = { |
| 4365 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 4366 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 4367 | }; |
| 4368 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4369 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4370 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 4371 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 4372 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4373 | } |
| 4374 | } |
| 4375 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 4376 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4377 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4378 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4379 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4380 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4381 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4382 | } |
| 4383 | } |
| 4384 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4385 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4386 | { |
| 4387 | int channel; |
| 4388 | |
| 4389 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4390 | /* Always drive command bus */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4391 | MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4392 | } |
| 4393 | |
| 4394 | udelay(1); |
| 4395 | |
| 4396 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4397 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4398 | } |
| 4399 | } |
| 4400 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4401 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4402 | { |
| 4403 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 4404 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4405 | FOR_ALL_POPULATED_CHANNELS { |
| 4406 | u32 b20, b4_8_12; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4407 | int min_pi = 10000; |
| 4408 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4409 | |
| 4410 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4411 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 4412 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4413 | } |
| 4414 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4415 | b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4416 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4417 | b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4418 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 4419 | dram_odt_stretch(ctrl, channel); |
| 4420 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4421 | MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 4422 | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4423 | } |
| 4424 | } |
| 4425 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4426 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4427 | { |
| 4428 | int channel; |
| 4429 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4430 | MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; |
| 4431 | MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4432 | } |
| 4433 | } |
| 4434 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4435 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 4436 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4437 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4438 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4439 | } |
| 4440 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4441 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4442 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4443 | { |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 4444 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
| 4445 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4446 | int channel; |
| 4447 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 4448 | int t3_ns; |
| 4449 | u32 r32; |
| 4450 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4451 | /* FIXME: This register only exists on Ivy Bridge */ |
| 4452 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4453 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 4454 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4455 | MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 4456 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 4457 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 4458 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 4459 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 4460 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4461 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 4462 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 4463 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 4464 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4465 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 4466 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4467 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 4468 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4469 | |
| 4470 | FOR_ALL_CHANNELS { |
| 4471 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4472 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4473 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4474 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4475 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4476 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4477 | case 1: |
| 4478 | case 4: |
| 4479 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4480 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4481 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4482 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4483 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4484 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4485 | break; |
| 4486 | } |
| 4487 | } |
| 4488 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 4489 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4490 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 4491 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 4492 | |
| 4493 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4494 | MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4495 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4496 | MCHBAR32_OR(MC_INIT_STATE_G, 1); |
| 4497 | MCHBAR32_OR(MC_INIT_STATE_G, 0x80); |
| 4498 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4499 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4500 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4501 | FOR_ALL_POPULATED_CHANNELS |
| 4502 | break; |
| 4503 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4504 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 4505 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4506 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4507 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4508 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4509 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4510 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4511 | t1_ns += 500; |
| 4512 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4513 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 4514 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4515 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4516 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 4517 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4518 | t3_ns = 500; |
| 4519 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4520 | |
| 4521 | /* The graphics driver will use these watermark values */ |
| 4522 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
| 4523 | MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, |
| 4524 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 4525 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4526 | } |
| 4527 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4528 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4529 | { |
| 4530 | int channel, slotrank, lane; |
| 4531 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4532 | FOR_ALL_POPULATED_CHANNELS { |
| 4533 | MCHBAR32(TC_RAP_ch(channel)) = |
| 4534 | (ctrl->tRRD << 0) |
| 4535 | | (ctrl->tRTP << 4) |
| 4536 | | (ctrl->tCKE << 8) |
| 4537 | | (ctrl->tWTR << 12) |
| 4538 | | (ctrl->tFAW << 16) |
| 4539 | | (ctrl->tWR << 24) |
| 4540 | | (ctrl->cmd_stretch[channel] << 30); |
| 4541 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4542 | |
| 4543 | udelay(1); |
| 4544 | |
| 4545 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4546 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4547 | } |
| 4548 | |
| 4549 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4550 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4551 | } |
| 4552 | |
| 4553 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4554 | MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4555 | |
| 4556 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4557 | udelay(1); |
| 4558 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4559 | } |
| 4560 | |
| 4561 | printram("CPE\n"); |
| 4562 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4563 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 4564 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4565 | |
| 4566 | printram("CP5b\n"); |
| 4567 | |
| 4568 | FOR_ALL_POPULATED_CHANNELS { |
| 4569 | program_timings(ctrl, channel); |
| 4570 | } |
| 4571 | |
| 4572 | u32 reg, addr; |
| 4573 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4574 | /* Poll for RCOMP */ |
| 4575 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 4576 | ; |
| 4577 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4578 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4579 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4580 | } while ((reg & 0x14) == 0); |
| 4581 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4582 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4583 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4584 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4585 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4586 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4587 | udelay(500); |
| 4588 | |
| 4589 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4590 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4591 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4592 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4593 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4594 | MCHBAR32(addr) = reg; |
| 4595 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4596 | /* Wait 10ns for ranks to settle */ |
| 4597 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4598 | |
| 4599 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 4600 | MCHBAR32(addr) = reg; |
| 4601 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4602 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4603 | write_reset(ctrl); |
| 4604 | } |
| 4605 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 4606 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4607 | dram_mrscommands(ctrl); |
| 4608 | |
| 4609 | printram("CP5c\n"); |
| 4610 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4611 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4612 | |
| 4613 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 4614 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4615 | udelay(2); |
| 4616 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4617 | } |