Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
| 17 | #include <stdlib.h> |
| 18 | #include <console/console.h> |
| 19 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 22 | #include <cbmem.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 23 | #include <halt.h> |
Kyösti Mälkki | 8183025 | 2016-06-25 11:40:00 +0300 | [diff] [blame] | 24 | #include <romstage_handoff.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 25 | #include "i945.h" |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 27 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 28 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 29 | int i945_silicon_revision(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 30 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 31 | return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 34 | static void i945m_detect_chipset(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 35 | { |
| 36 | u8 reg8; |
| 37 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 38 | printk(BIOS_INFO, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 39 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4; |
| 40 | switch (reg8) { |
| 41 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 42 | printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 43 | break; |
| 44 | case 2: |
Stefan Reinauer | 7981b94 | 2011-04-01 22:33:25 +0200 | [diff] [blame] | 45 | printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 46 | break; |
| 47 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 48 | printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 49 | break; |
| 50 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 51 | printk(BIOS_INFO, "Intel(R) 82945GT Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 52 | break; |
| 53 | case 6: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 54 | printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 55 | break; |
| 56 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 57 | printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 58 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 59 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 60 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 61 | printk(BIOS_DEBUG, "(G)MCH capable of up to FSB "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 62 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5; |
| 63 | switch (reg8) { |
| 64 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 65 | printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 66 | break; |
| 67 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 68 | printk(BIOS_DEBUG, "667 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 69 | break; |
| 70 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "533 MHz"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 72 | break; |
| 73 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 75 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 76 | printk(BIOS_DEBUG, "\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 77 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 78 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 79 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 80 | switch (reg8) { |
| 81 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 82 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | break; |
| 84 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 86 | break; |
| 87 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 88 | printk(BIOS_DEBUG, "DDR2-400"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 89 | break; |
| 90 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 91 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 92 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 93 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 94 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 95 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 96 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 97 | } |
| 98 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 99 | static void i945_detect_chipset(void) |
| 100 | { |
| 101 | u8 reg8; |
| 102 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 103 | printk(BIOS_INFO, "\nIntel(R) "); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 104 | |
| 105 | reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 106 | switch (reg8) { |
| 107 | case 0: |
| 108 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 109 | printk(BIOS_INFO, "82945G"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 110 | break; |
| 111 | case 2: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 112 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 113 | printk(BIOS_INFO, "82945P"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 114 | break; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 115 | case 4: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 116 | printk(BIOS_INFO, "82945GC"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 117 | break; |
| 118 | case 5: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 119 | printk(BIOS_INFO, "82945GZ"); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 120 | break; |
| 121 | case 6: |
| 122 | case 7: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 123 | printk(BIOS_INFO, "82945PL"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 124 | break; |
| 125 | default: |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 126 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 127 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 128 | printk(BIOS_INFO, " Chipset\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 129 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "(G)MCH capable of "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 131 | reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); |
| 132 | switch (reg8) { |
| 133 | case 0: |
Elyes HAOUAS | 5db9450 | 2016-10-30 18:30:21 +0100 | [diff] [blame] | 134 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 135 | printk(BIOS_DEBUG, "up to DDR2-667"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 136 | break; |
| 137 | case 3: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 138 | printk(BIOS_DEBUG, "up to DDR2-533"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 139 | break; |
| 140 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 141 | printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 142 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 143 | printk(BIOS_DEBUG, "\n"); |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 144 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 145 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Elyes HAOUAS | 6372a0e | 2016-10-30 18:39:53 +0100 | [diff] [blame] | 146 | printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 147 | } |
| 148 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 149 | static void i945_setup_bars(void) |
| 150 | { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 151 | u8 reg8, gfxsize; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 152 | |
| 153 | /* As of now, we don't have all the A0 workarounds implemented */ |
| 154 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 155 | printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 156 | |
| 157 | /* Setting up Southbridge. In the northbridge code. */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 158 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 159 | |
| 160 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 161 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 162 | |
| 163 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 164 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 165 | setup_pch_gpios(&mainboard_gpio_map); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 166 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 167 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 168 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 169 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 170 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
Nico Huber | 0b80bd1 | 2017-09-09 19:46:44 +0200 | [diff] [blame] | 171 | outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ |
| 172 | outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 173 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 174 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 175 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 176 | /* Set up all hardcoded northbridge BARs */ |
| 177 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 178 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 179 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 180 | pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); |
| 181 | |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 182 | /* vram size from cmos option */ |
| 183 | if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) |
| 184 | gfxsize = 2; /* 2 for 8MB */ |
| 185 | /* make sure no invalid setting is used */ |
| 186 | if (gfxsize > 6) |
| 187 | gfxsize = 2; |
| 188 | pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 189 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 190 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
Arthur Heymans | e07df9d | 2018-04-09 22:03:21 +0200 | [diff] [blame] | 191 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); |
| 192 | reg8 &= ~0x7; |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 193 | reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ |
Arthur Heymans | e07df9d | 2018-04-09 22:03:21 +0200 | [diff] [blame] | 194 | pci_write_config8(PCI_DEV(0, 0, 0), ESMRAMC, reg8); |
| 195 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 196 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 197 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 198 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 199 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 200 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 201 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 202 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 203 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 204 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 205 | printk(BIOS_DEBUG, " done.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 206 | |
| 207 | /* Wait for MCH BAR to come up */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 208 | printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); |
Elyes HAOUAS | a3ea1e4 | 2014-11-27 13:23:32 +0100 | [diff] [blame] | 209 | if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 210 | do { |
| 211 | reg8 = *(volatile u8 *)0xfed40000; |
| 212 | } while (!(reg8 & 0x80)); |
| 213 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 214 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | static void i945_setup_egress_port(void) |
| 218 | { |
| 219 | u32 reg32; |
| 220 | u32 timeout; |
| 221 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 222 | printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 223 | |
| 224 | /* Egress Port Virtual Channel 0 Configuration */ |
| 225 | |
| 226 | /* map only TC0 to VC0 */ |
| 227 | reg32 = EPBAR32(EPVC0RCTL); |
| 228 | reg32 &= 0xffffff01; |
| 229 | EPBAR32(EPVC0RCTL) = reg32; |
| 230 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 231 | reg32 = EPBAR32(EPPVCCAP1); |
| 232 | reg32 &= ~(7 << 0); |
| 233 | reg32 |= 1; |
| 234 | EPBAR32(EPPVCCAP1) = reg32; |
| 235 | |
| 236 | /* Egress Port Virtual Channel 1 Configuration */ |
| 237 | reg32 = EPBAR32(0x2c); |
| 238 | reg32 &= 0xffffff00; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 239 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 240 | if ((MCHBAR32(CLKCFG) & 7) == 0) |
| 241 | reg32 |= 0x1a; /* 1067MHz */ |
| 242 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 243 | if ((MCHBAR32(CLKCFG) & 7) == 1) |
| 244 | reg32 |= 0x0d; /* 533MHz */ |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 245 | if ((MCHBAR32(CLKCFG) & 7) == 2) |
| 246 | reg32 |= 0x14; /* 800MHz */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 247 | if ((MCHBAR32(CLKCFG) & 7) == 3) |
| 248 | reg32 |= 0x10; /* 667MHz */ |
| 249 | EPBAR32(0x2c) = reg32; |
| 250 | |
| 251 | EPBAR32(EPVC1MTS) = 0x0a0a0a0a; |
| 252 | |
| 253 | reg32 = EPBAR32(EPVC1RCAP); |
| 254 | reg32 &= ~(0x7f << 16); |
| 255 | reg32 |= (0x0a << 16); |
| 256 | EPBAR32(EPVC1RCAP) = reg32; |
| 257 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 258 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 259 | if ((MCHBAR32(CLKCFG) & 7) == 0) { /* 1067MHz */ |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 260 | EPBAR32(EPVC1IST + 0) = 0x01380138; |
| 261 | EPBAR32(EPVC1IST + 4) = 0x01380138; |
| 262 | } |
| 263 | } |
| 264 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 265 | if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */ |
| 266 | EPBAR32(EPVC1IST + 0) = 0x009c009c; |
| 267 | EPBAR32(EPVC1IST + 4) = 0x009c009c; |
| 268 | } |
| 269 | |
Elyes HAOUAS | f7acdf8 | 2016-10-31 18:55:04 +0100 | [diff] [blame] | 270 | if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ |
| 271 | EPBAR32(EPVC1IST + 0) = 0x00f000f0; |
| 272 | EPBAR32(EPVC1IST + 4) = 0x00f000f0; |
| 273 | } |
| 274 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 275 | if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ |
| 276 | EPBAR32(EPVC1IST + 0) = 0x00c000c0; |
| 277 | EPBAR32(EPVC1IST + 4) = 0x00c000c0; |
| 278 | } |
| 279 | |
| 280 | /* Is internal graphics enabled? */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 281 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 282 | MCHBAR32(MMARB1) |= (1 << 17); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 283 | |
| 284 | /* Assign Virtual Channel ID 1 to VC1 */ |
| 285 | reg32 = EPBAR32(EPVC1RCTL); |
| 286 | reg32 &= ~(7 << 24); |
| 287 | reg32 |= (1 << 24); |
| 288 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 289 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 290 | reg32 = EPBAR32(EPVC1RCTL); |
| 291 | reg32 &= 0xffffff01; |
| 292 | reg32 |= (1 << 7); |
| 293 | EPBAR32(EPVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 294 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 295 | EPBAR32(PORTARB + 0x00) = 0x01000001; |
| 296 | EPBAR32(PORTARB + 0x04) = 0x00040000; |
| 297 | EPBAR32(PORTARB + 0x08) = 0x00001000; |
| 298 | EPBAR32(PORTARB + 0x0c) = 0x00000040; |
| 299 | EPBAR32(PORTARB + 0x10) = 0x01000001; |
| 300 | EPBAR32(PORTARB + 0x14) = 0x00040000; |
| 301 | EPBAR32(PORTARB + 0x18) = 0x00001000; |
| 302 | EPBAR32(PORTARB + 0x1c) = 0x00000040; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 303 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 304 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 305 | EPBAR32(EPVC1RCTL) |= (1 << 16); |
| 306 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 307 | printk(BIOS_DEBUG, "Loading port arbitration table ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 308 | /* Loop until bit 0 becomes 0 */ |
| 309 | timeout = 0x7fffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 310 | while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) |
| 311 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 312 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 313 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 314 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 315 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 316 | |
| 317 | /* Now enable VC1 */ |
| 318 | EPBAR32(EPVC1RCTL) |= (1 << 31); |
| 319 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 320 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 321 | /* Wait for VC1 negotiation pending */ |
| 322 | timeout = 0x7fff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 323 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) |
| 324 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 325 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 326 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 327 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 328 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 329 | |
| 330 | } |
| 331 | |
| 332 | static void ich7_setup_dmi_rcrb(void) |
| 333 | { |
| 334 | u16 reg16; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 335 | u32 reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 336 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 337 | reg16 = RCBA16(LCTL); |
| 338 | reg16 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 339 | reg16 |= 3; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 340 | RCBA16(LCTL) = reg16; |
| 341 | |
| 342 | RCBA32(V0CTL) = 0x80000001; |
| 343 | RCBA32(V1CAP) = 0x03128010; |
| 344 | RCBA32(ESD) = 0x00000810; |
| 345 | RCBA32(RP1D) = 0x01000003; |
| 346 | RCBA32(RP2D) = 0x02000002; |
| 347 | RCBA32(RP3D) = 0x03000002; |
| 348 | RCBA32(RP4D) = 0x04000002; |
| 349 | RCBA32(HDD) = 0x0f000003; |
| 350 | RCBA32(RP5D) = 0x05000002; |
| 351 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 352 | pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141); |
| 353 | pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141); |
| 354 | pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 355 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 356 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 357 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 358 | |
| 359 | reg32 = RCBA32(V1CTL); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 360 | reg32 &= ~((0x7f << 1) | (7 << 17) | (7 << 24)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 361 | reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31); |
| 362 | RCBA32(V1CTL) = reg32; |
| 363 | |
| 364 | RCBA32(ESD) |= (2 << 16); |
| 365 | |
| 366 | RCBA32(ULD) |= (1 << 24) | (1 << 16); |
| 367 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 368 | RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 369 | |
| 370 | RCBA32(RP1D) |= (2 << 16); |
| 371 | RCBA32(RP2D) |= (2 << 16); |
| 372 | RCBA32(RP3D) |= (2 << 16); |
| 373 | RCBA32(RP4D) |= (2 << 16); |
| 374 | RCBA32(HDD) |= (2 << 16); |
| 375 | RCBA32(RP5D) |= (2 << 16); |
| 376 | RCBA32(RP6D) |= (2 << 16); |
| 377 | |
| 378 | RCBA32(LCAP) |= (3 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 379 | } |
| 380 | |
| 381 | static void i945_setup_dmi_rcrb(void) |
| 382 | { |
| 383 | u32 reg32; |
| 384 | u32 timeout; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 385 | int activate_aspm = 1; /* hardcode ASPM for now */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 386 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 387 | printk(BIOS_DEBUG, "Setting up DMI RCRB\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 388 | |
| 389 | /* Virtual Channel 0 Configuration */ |
| 390 | reg32 = DMIBAR32(DMIVC0RCTL0); |
| 391 | reg32 &= 0xffffff01; |
| 392 | DMIBAR32(DMIVC0RCTL0) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 393 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 394 | reg32 = DMIBAR32(DMIPVCCAP1); |
| 395 | reg32 &= ~(7 << 0); |
| 396 | reg32 |= 1; |
| 397 | DMIBAR32(DMIPVCCAP1) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 398 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 399 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 400 | reg32 &= ~(7 << 24); |
| 401 | reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */ |
| 402 | DMIBAR32(DMIVC1RCTL) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 403 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 404 | reg32 = DMIBAR32(DMIVC1RCTL); |
| 405 | reg32 &= 0xffffff01; |
| 406 | reg32 |= (1 << 7); |
| 407 | DMIBAR32(DMIVC1RCTL) = reg32; |
| 408 | |
| 409 | /* Now enable VC1 */ |
| 410 | DMIBAR32(DMIVC1RCTL) |= (1 << 31); |
| 411 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 412 | printk(BIOS_DEBUG, "Wait for VC1 negotiation ..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 413 | /* Wait for VC1 negotiation pending */ |
| 414 | timeout = 0x7ffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 415 | while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) |
| 416 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 417 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 418 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 419 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 420 | printk(BIOS_DEBUG, "done..\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 421 | #if 1 |
| 422 | /* Enable Active State Power Management (ASPM) L0 state */ |
| 423 | |
| 424 | reg32 = DMIBAR32(DMILCAP); |
| 425 | reg32 &= ~(7 << 12); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 426 | reg32 |= (2 << 12); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 427 | |
| 428 | reg32 &= ~(7 << 15); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 429 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 430 | reg32 |= (2 << 15); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 431 | DMIBAR32(DMILCAP) = reg32; |
| 432 | |
| 433 | reg32 = DMIBAR32(DMICC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 434 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 435 | reg32 &= ~(3 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 436 | reg32 |= (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 437 | reg32 &= ~(3 << 20); |
| 438 | reg32 |= (1 << 20); |
| 439 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 440 | DMIBAR32(DMICC) = reg32; |
| 441 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 442 | if (activate_aspm) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 443 | DMIBAR32(DMILCTL) |= (3 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 444 | #endif |
| 445 | |
| 446 | /* Last but not least, some additional steps */ |
| 447 | reg32 = MCHBAR32(FSBSNPCTL); |
| 448 | reg32 &= ~(0xff << 2); |
| 449 | reg32 |= (0xaa << 2); |
| 450 | MCHBAR32(FSBSNPCTL) = reg32; |
| 451 | |
| 452 | DMIBAR32(0x2c) = 0x86000040; |
| 453 | |
| 454 | reg32 = DMIBAR32(0x204); |
| 455 | reg32 &= ~0x3ff; |
| 456 | #if 1 |
| 457 | reg32 |= 0x13f; /* for x4 DMI only */ |
| 458 | #else |
| 459 | reg32 |= 0x1e4; /* for x2 DMI only */ |
| 460 | #endif |
| 461 | DMIBAR32(0x204) = reg32; |
| 462 | |
Kyösti Mälkki | 3c3e34d | 2014-05-31 11:32:54 +0300 | [diff] [blame] | 463 | if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 464 | printk(BIOS_DEBUG, "Internal graphics: enabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 465 | DMIBAR32(0x200) |= (1 << 21); |
| 466 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 467 | printk(BIOS_DEBUG, "Internal graphics: disabled\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 468 | DMIBAR32(0x200) &= ~(1 << 21); |
| 469 | } |
| 470 | |
| 471 | reg32 = DMIBAR32(0x204); |
| 472 | reg32 &= ~((1 << 11) | (1 << 10)); |
| 473 | DMIBAR32(0x204) = reg32; |
| 474 | |
| 475 | reg32 = DMIBAR32(0x204); |
| 476 | reg32 &= ~(0xff << 12); |
| 477 | reg32 |= (0x0d << 12); |
| 478 | DMIBAR32(0x204) = reg32; |
| 479 | |
| 480 | DMIBAR32(DMICTL1) |= (3 << 24); |
| 481 | |
| 482 | reg32 = DMIBAR32(0x200); |
| 483 | reg32 &= ~(0x3 << 26); |
| 484 | reg32 |= (0x02 << 26); |
| 485 | DMIBAR32(0x200) = reg32; |
| 486 | |
| 487 | DMIBAR32(DMIDRCCFG) &= ~(1 << 31); |
| 488 | DMIBAR32(DMICTL2) |= (1 << 31); |
| 489 | |
| 490 | if (i945_silicon_revision() >= 3) { |
| 491 | reg32 = DMIBAR32(0xec0); |
| 492 | reg32 &= 0x0fffffff; |
| 493 | reg32 |= (2 << 28); |
| 494 | DMIBAR32(0xec0) = reg32; |
| 495 | |
| 496 | reg32 = DMIBAR32(0xed4); |
| 497 | reg32 &= 0x0fffffff; |
| 498 | reg32 |= (2 << 28); |
| 499 | DMIBAR32(0xed4) = reg32; |
| 500 | |
| 501 | reg32 = DMIBAR32(0xee8); |
| 502 | reg32 &= 0x0fffffff; |
| 503 | reg32 |= (2 << 28); |
| 504 | DMIBAR32(0xee8) = reg32; |
| 505 | |
| 506 | reg32 = DMIBAR32(0xefc); |
| 507 | reg32 &= 0x0fffffff; |
| 508 | reg32 |= (2 << 28); |
| 509 | DMIBAR32(0xefc) = reg32; |
| 510 | } |
| 511 | |
| 512 | /* wait for bit toggle to 0 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 513 | printk(BIOS_DEBUG, "Waiting for DMI hardware..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 514 | timeout = 0x7fffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 515 | while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) |
| 516 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 517 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 518 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 519 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 520 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 521 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 522 | /* Clear Error Status Bits! */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 523 | DMIBAR32(0x1c4) = 0xffffffff; |
| 524 | DMIBAR32(0x1d0) = 0xffffffff; |
| 525 | DMIBAR32(0x228) = 0xffffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 526 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 527 | /* Program Read-Only Write-Once Registers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 528 | DMIBAR32(0x308) = DMIBAR32(0x308); |
| 529 | DMIBAR32(0x314) = DMIBAR32(0x314); |
| 530 | DMIBAR32(0x324) = DMIBAR32(0x324); |
| 531 | DMIBAR32(0x328) = DMIBAR32(0x328); |
Elyes HAOUAS | d3fa7fa5 | 2019-01-24 11:47:27 +0100 | [diff] [blame] | 532 | DMIBAR32(0x334) = DMIBAR32(0x334); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 533 | DMIBAR32(0x338) = DMIBAR32(0x338); |
| 534 | |
Patrick Georgi | a341a77 | 2014-09-29 19:51:21 +0200 | [diff] [blame] | 535 | if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 536 | if ((MCHBAR32(0x214) & 0xf) != 0x3) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 537 | printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 538 | reg32 = DMIBAR32(0x224); |
| 539 | reg32 &= ~(7 << 0); |
| 540 | reg32 |= (3 << 0); |
| 541 | DMIBAR32(0x224) = reg32; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 542 | outb(0x06, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 543 | halt(); /* wait for reset */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 544 | } |
| 545 | } |
| 546 | } |
| 547 | |
| 548 | static void i945_setup_pci_express_x16(void) |
| 549 | { |
| 550 | u32 timeout; |
| 551 | u32 reg32; |
| 552 | u16 reg16; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 553 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 554 | printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 555 | |
| 556 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 557 | reg16 |= DEVEN_D1F0; |
| 558 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 559 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 560 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGCC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 561 | reg32 &= ~(1 << 8); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 562 | pci_write_config32(PCI_DEV(0, 0x01, 0), PEGCC, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 563 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 564 | /* We have no success with querying the usual PCIe registers |
| 565 | * for link setup success on the i945. Hence we assign a temporary |
| 566 | * PCI bus 0x0a and check whether we find a device on 0:a.0 |
| 567 | */ |
| 568 | |
| 569 | /* First we reset the secondary bus */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 570 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 571 | reg16 |= (1 << 6); /* SRESET */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 572 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 573 | /* Read back and clear reset bit. */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 574 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 575 | reg16 &= ~(1 << 6); /* SRESET */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 576 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 577 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 578 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 579 | printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 580 | if (!(reg16 & 0x48)) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 581 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 582 | reg16 |= (1 << 4) | (1 << 0); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 583 | pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 584 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 585 | pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00); |
| 586 | pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00); |
| 587 | pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a); |
| 588 | pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 589 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 590 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 591 | reg32 &= ~(1 << 8); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 592 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 593 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 594 | MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0)); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 595 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 596 | /* Initialize PEG_CAP */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 597 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PEG_CAP); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 598 | reg16 |= (1 << 8); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 599 | pci_write_config16(PCI_DEV(0, 0x01, 0), PEG_CAP, reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 600 | |
| 601 | /* Setup SLOTCAP */ |
| 602 | /* TODO: These values are mainboard dependent and should |
Uwe Hermann | 607614d | 2010-11-18 20:12:13 +0000 | [diff] [blame] | 603 | * be set from devicetree.cb. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 604 | */ |
| 605 | /* NOTE: SLOTCAP becomes RO after the first write! */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 606 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), SLOTCAP); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 607 | reg32 &= 0x0007ffff; |
| 608 | |
| 609 | reg32 &= 0xfffe007f; |
| 610 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 611 | pci_write_config32(PCI_DEV(0, 0x01, 0), SLOTCAP, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 612 | |
| 613 | /* Wait for training to succeed */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 614 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 615 | timeout = 0x7ffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 616 | while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) |
| 617 | && --timeout) |
| 618 | ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 619 | |
| 620 | reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); |
| 621 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 622 | printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 623 | reg32 & 0xffff, reg32 >> 16); |
| 624 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 625 | printk(BIOS_DEBUG, " timeout!\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 626 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 627 | printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 628 | |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 629 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 630 | reg32 &= ~(0xf << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 631 | reg32 |= 1; |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 632 | pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 633 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 634 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 635 | |
| 636 | reg16 |= (1 << 6); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 637 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 638 | reg16 &= ~(1 << 6); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 639 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 640 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 641 | printk(BIOS_DEBUG, "PCIe link training ..."); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 642 | timeout = 0x7ffff; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 643 | while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) |
| 644 | && --timeout) |
| 645 | ; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 646 | |
| 647 | reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); |
| 648 | if (reg32 != 0x00000000 && reg32 != 0xffffffff) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 649 | printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 650 | reg32 & 0xffff, reg32 >> 16); |
| 651 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 652 | printk(BIOS_DEBUG, " timeout!\n"); |
| 653 | printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n"); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 654 | goto disable_pciexpress_x16_link; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 655 | } |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 656 | } |
| 657 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 658 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 659 | reg16 >>= 4; |
| 660 | reg16 &= 0x3f; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 661 | /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 662 | printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 663 | |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 664 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGTC); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 665 | reg32 &= 0xfffffc00; /* clear [9:0] */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 666 | if (reg16 == 1) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 667 | reg32 |= 0x32b; |
| 668 | // TODO |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 669 | /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 670 | else if (reg16 == 16) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 671 | reg32 |= 0x0f4; |
| 672 | // TODO |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 673 | /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 674 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 675 | reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 676 | printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 677 | if (reg32 == 0x030000) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 678 | printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 679 | reg16 = (1 << 1); |
Elyes HAOUAS | ef20ecc | 2018-10-04 13:50:14 +0200 | [diff] [blame] | 680 | pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 681 | |
Kyösti Mälkki | 3c3e34d | 2014-05-31 11:32:54 +0300 | [diff] [blame] | 682 | reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); |
| 683 | reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); |
| 684 | pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 685 | |
| 686 | /* Set VGA enable bit in PCIe bridge */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 687 | reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), BCTRL1); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 688 | reg16 |= (1 << 3); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 689 | pci_write_config16(PCI_DEV(0, 0x1, 0), BCTRL1, reg16); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 690 | } |
| 691 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 692 | /* Enable GPEs */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 693 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEG_LC); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 694 | reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 695 | pci_write_config32(PCI_DEV(0, 0x01, 0), PEG_LC, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 696 | |
| 697 | /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 698 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), VC0RCTL); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 699 | reg32 &= 0xffffff01; |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 700 | pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 701 | |
| 702 | /* Extended VC count */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 703 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PVCCAP1); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 704 | reg32 &= ~(7 << 0); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 705 | pci_write_config32(PCI_DEV(0, 0x01, 0), PVCCAP1, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 706 | |
| 707 | /* Active State Power Management ASPM */ |
| 708 | |
| 709 | /* TODO */ |
| 710 | |
| 711 | /* Clear error bits */ |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 712 | pci_write_config16(PCI_DEV(0, 0x01, 0), PCISTS1, 0xffff); |
| 713 | pci_write_config16(PCI_DEV(0, 0x01, 0), SSTS1, 0xffff); |
| 714 | pci_write_config16(PCI_DEV(0, 0x01, 0), DSTS, 0xffff); |
| 715 | pci_write_config32(PCI_DEV(0, 0x01, 0), UESTS, 0xffffffff); |
| 716 | pci_write_config32(PCI_DEV(0, 0x01, 0), CESTS, 0xffffffff); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 717 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); |
| 718 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 719 | |
| 720 | /* Program R/WO registers */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 721 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308); |
| 722 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 723 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 724 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314); |
| 725 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 726 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 727 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324); |
| 728 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 729 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 730 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); |
| 731 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 732 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 733 | /* Additional PCIe graphics setup */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 734 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 735 | reg32 |= (3 << 26); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 736 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 737 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 738 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 739 | reg32 |= (3 << 24); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 740 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 741 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 742 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 743 | reg32 |= (1 << 5); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 744 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 745 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 746 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 747 | reg32 &= ~(3 << 26); |
| 748 | reg32 |= (2 << 26); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 749 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 750 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 751 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 752 | if (i945_silicon_revision() >= 2) |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 753 | reg32 |= (1 << 12); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 754 | else |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 755 | reg32 &= ~(1 << 12); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 756 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 757 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 758 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 759 | reg32 &= ~(1 << 31); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 760 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 761 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 762 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 763 | reg32 |= (1 << 31); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 764 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 765 | |
| 766 | if (i945_silicon_revision() >= 3) { |
| 767 | static const u32 reglist[] = { |
| 768 | 0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24, |
| 769 | 0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c, |
| 770 | 0xfb0, 0xfc4, 0xfd8, 0xfec |
| 771 | }; |
| 772 | |
| 773 | int i; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 774 | for (i = 0; i < ARRAY_SIZE(reglist); i++) { |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 775 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 776 | reg32 &= 0x0fffffff; |
| 777 | reg32 |= (2 << 28); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 778 | pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 779 | } |
| 780 | } |
| 781 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 782 | if (i945_silicon_revision() <= 2) { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 783 | /* Set voltage specific parameters */ |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 784 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 785 | reg32 &= (0xf << 4); /* Default case 1.05V */ |
Patrick Georgi | 3cb86de | 2014-09-29 20:42:33 +0200 | [diff] [blame] | 786 | if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 787 | reg32 |= (7 << 4); |
| 788 | } |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 789 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 790 | } |
| 791 | |
| 792 | return; |
| 793 | |
| 794 | disable_pciexpress_x16_link: |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 795 | /* For now we just disable the x16 link */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 796 | printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 797 | |
| 798 | MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); |
| 799 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 800 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 801 | reg16 |= (1 << 6); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 802 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 803 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 804 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 805 | reg32 |= (1 << 8); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 806 | pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 807 | |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 808 | reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 809 | reg16 &= ~(1 << 6); |
Kyösti Mälkki | 8aa7e83 | 2013-07-26 08:52:10 +0300 | [diff] [blame] | 810 | pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 811 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 812 | printk(BIOS_DEBUG, "Wait for link to enter detect state... "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 813 | timeout = 0x7fffff; |
Patrick Georgi | d3060ed | 2014-08-10 15:19:45 +0200 | [diff] [blame] | 814 | for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 815 | (reg32 & 0x000f0000) && --timeout;) |
| 816 | ; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 817 | if (!timeout) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 818 | printk(BIOS_DEBUG, "timeout!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 819 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 820 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 821 | |
| 822 | /* Finally: Disable the PCI config header */ |
| 823 | reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); |
| 824 | reg16 &= ~DEVEN_D1F0; |
| 825 | pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); |
| 826 | } |
| 827 | |
| 828 | static void i945_setup_root_complex_topology(void) |
| 829 | { |
| 830 | u32 reg32; |
| 831 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 832 | printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 833 | /* Egress Port Root Topology */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 834 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 835 | reg32 = EPBAR32(EPESD); |
| 836 | reg32 &= 0xff00ffff; |
| 837 | reg32 |= (1 << 16); |
| 838 | EPBAR32(EPESD) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 839 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 840 | EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 841 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 842 | EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 843 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 844 | EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 845 | |
| 846 | /* DMI Port Root Topology */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 847 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 848 | reg32 = DMIBAR32(DMILE1D); |
| 849 | reg32 &= 0x00ffffff; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 850 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 851 | reg32 &= 0xff00ffff; |
| 852 | reg32 |= (2 << 16); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 853 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 854 | reg32 |= (1 << 0); |
| 855 | DMIBAR32(DMILE1D) = reg32; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 856 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 857 | DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 858 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 859 | DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 860 | |
| 861 | DMIBAR32(DMILE2A) = DEFAULT_EPBAR; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 862 | |
| 863 | /* PCI Express x16 Port Root Topology */ |
| 864 | if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 865 | pci_write_config32(PCI_DEV(0, 0x01, 0), LE1A, DEFAULT_EPBAR); |
| 866 | reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), LE1D); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 867 | reg32 |= (1 << 0); |
Elyes HAOUAS | a6634f1 | 2018-11-24 10:26:04 +0100 | [diff] [blame] | 868 | pci_write_config32(PCI_DEV(0, 0x01, 0), LE1D, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 869 | } |
| 870 | } |
| 871 | |
| 872 | static void ich7_setup_root_complex_topology(void) |
| 873 | { |
| 874 | RCBA32(0x104) = 0x00000802; |
| 875 | RCBA32(0x110) = 0x00000001; |
| 876 | RCBA32(0x114) = 0x00000000; |
| 877 | RCBA32(0x118) = 0x00000000; |
| 878 | } |
| 879 | |
| 880 | static void ich7_setup_pci_express(void) |
| 881 | { |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 882 | RCBA32(CG) |= (1 << 0); |
| 883 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 884 | /* Initialize slot power limit for root ports */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 885 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 886 | #if 0 |
| 887 | pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0); |
| 888 | pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0); |
| 889 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 890 | |
| 891 | pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); |
| 892 | } |
| 893 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 894 | void i945_early_initialization(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 895 | { |
| 896 | /* Print some chipset specific information */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 897 | switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 898 | case 0x27708086: /* 82945G/GZ/GC/P/PL */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 899 | i945_detect_chipset(); |
| 900 | break; |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 901 | case 0x27a08086: /* 945GME/GSE */ |
| 902 | case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 903 | i945m_detect_chipset(); |
| 904 | break; |
| 905 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 906 | |
| 907 | /* Setup all BARs required for early PCIe and raminit */ |
| 908 | i945_setup_bars(); |
| 909 | |
| 910 | /* Change port80 to LPC */ |
| 911 | RCBA32(GCS) &= (~0x04); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 912 | |
| 913 | /* Just do it that way */ |
| 914 | RCBA32(0x2010) |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 915 | } |
| 916 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 917 | static void i945_prepare_resume(int s3resume) |
| 918 | { |
| 919 | int cbmem_was_initted; |
| 920 | |
| 921 | cbmem_was_initted = !cbmem_recovery(s3resume); |
| 922 | |
Kyösti Mälkki | 8183025 | 2016-06-25 11:40:00 +0300 | [diff] [blame] | 923 | romstage_handoff_init(cbmem_was_initted && s3resume); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 924 | } |
| 925 | |
| 926 | void i945_late_initialization(int s3resume) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 927 | { |
| 928 | i945_setup_egress_port(); |
| 929 | |
| 930 | ich7_setup_root_complex_topology(); |
| 931 | |
| 932 | ich7_setup_pci_express(); |
| 933 | |
| 934 | ich7_setup_dmi_rcrb(); |
| 935 | |
| 936 | i945_setup_dmi_rcrb(); |
| 937 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 938 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 939 | i945_setup_pci_express_x16(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 940 | |
| 941 | i945_setup_root_complex_topology(); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 942 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 943 | #if !CONFIG(HAVE_ACPI_RESUME) |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 944 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 945 | #if CONFIG(DEBUG_RAM_SETUP) |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 946 | sdram_dump_mchbar_registers(); |
| 947 | |
| 948 | { |
| 949 | /* This will not work if TSEG is in place! */ |
Paul Menzel | 9d3e131 | 2014-06-05 08:50:17 +0200 | [diff] [blame] | 950 | u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 951 | |
| 952 | printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); |
| 953 | ram_check(0x00000000, 0x000a0000); |
| 954 | ram_check(0x00100000, tom); |
| 955 | } |
| 956 | #endif |
| 957 | #endif |
| 958 | #endif |
| 959 | |
| 960 | MCHBAR16(SSKPD) = 0xCAFE; |
| 961 | |
| 962 | i945_prepare_resume(s3resume); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 963 | } |