nb/intel/i945: Clear timeout bits after disabling watchdog
Even with the watchdog disabled, these bits influence other hardware
blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet
before they started).
Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 1d473d3..0abd42e 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -170,6 +170,8 @@
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */
+ outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */
printk(BIOS_DEBUG, " done.\n");
/* Enable upper 128bytes of CMOS */