Angel Pons | c80e350 | 2020-04-03 01:21:49 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 3 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 4 | #include <bootblock_common.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 5 | #include <stdint.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 6 | #include <arch/io.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 7 | #include <delay.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 8 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 10 | #include <option.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 11 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 12 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 13 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 14 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 15 | void mainboard_pre_raminit_config(int s3_resume) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 16 | { |
| 17 | u32 gpios; |
| 18 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 19 | printk(BIOS_SPEW, "\n Initializing drive bay...\n"); |
| 20 | gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 |
| 21 | gpios |= (1 << 0); // GPIO33 = ODD |
| 22 | gpios |= (1 << 1); // GPIO34 = IDE_RST# |
| 23 | outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ |
| 24 | |
| 25 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 26 | gpios &= ~(1 << 13); // ?? |
| 27 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 28 | |
| 29 | printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); |
| 30 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 31 | gpios &= ~(1 << 24); // Enable LAN Power |
| 32 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 33 | } |
| 34 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 35 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 36 | void mainboard_lpc_decode(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 37 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 38 | int lpt_en = 0; |
Kyösti Mälkki | bee82ab | 2019-12-26 10:57:43 +0200 | [diff] [blame] | 39 | u8 val; |
| 40 | |
| 41 | if (get_option(&val, "lpt") == CB_SUCCESS && val) |
| 42 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 43 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 44 | // decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 45 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 46 | // decode range |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 47 | pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 48 | } |
| 49 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 50 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 51 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 52 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 53 | * but safe anyways" method. |
| 54 | */ |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 55 | static void pnp_enter_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 56 | { |
| 57 | unsigned int port = dev >> 8; |
| 58 | outb(0x55, port); |
| 59 | } |
| 60 | |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 61 | static void pnp_exit_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 62 | { |
| 63 | unsigned int port = dev >> 8; |
| 64 | outb(0xaa, port); |
| 65 | } |
| 66 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 67 | void bootblock_mainboard_early_init(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 68 | { |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 69 | pnp_devfn_t dev; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 70 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 71 | dev = PNP_DEV(0x4e, 0x00); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 72 | |
| 73 | pnp_enter_ext_func_mode(dev); |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 74 | pnp_write_config(dev, 0x02, 0x0e); // UART power |
| 75 | pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base |
| 76 | pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base |
| 77 | pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ |
| 78 | pnp_write_config(dev, 0x1e, 1); // no 32khz clock |
| 79 | pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base |
| 80 | pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ |
| 81 | pnp_write_config(dev, 0x2c, 0); // DMA0 FIR |
| 82 | pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 83 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 84 | pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR |
| 85 | pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL |
| 86 | pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR |
| 87 | pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL |
| 88 | pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR |
| 89 | pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL |
| 90 | pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR |
| 91 | pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 92 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 93 | pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT |
| 94 | pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT |
| 95 | pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT |
| 96 | pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR |
| 97 | pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL |
| 98 | pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 |
| 99 | pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 |
| 100 | pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 101 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 102 | pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 |
| 103 | pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 |
| 104 | pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 |
| 105 | pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 |
| 106 | pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 |
| 107 | pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 108 | |
| 109 | pnp_exit_ext_func_mode(dev); |
| 110 | } |
| 111 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 112 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 113 | { |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 114 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 115 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 116 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 117 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 118 | |
| 119 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 120 | RCBA16(D31IR) = 0x0232; |
| 121 | RCBA16(D30IR) = 0x3246; |
| 122 | RCBA16(D29IR) = 0x0237; |
| 123 | RCBA16(D28IR) = 0x3201; |
| 124 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 125 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 126 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 127 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 128 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 129 | /* This should probably go into the ACPI enable trap */ |
| 130 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 131 | RCBA32(0x1e84) = 0x00020001; |
| 132 | RCBA32(0x1e80) = 0x0000fe01; |
| 133 | |
| 134 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 135 | RCBA32(0x1e9c) = 0x000200f0; |
| 136 | RCBA32(0x1e98) = 0x000c0801; |
| 137 | } |