Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 3 | * |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 17 | #include <bootblock_common.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 19 | #include <arch/io.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 20 | #include <delay.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 21 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 23 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 24 | #include <console/console.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 25 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 26 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 27 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 28 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 29 | void mainboard_pre_raminit_config(int s3_resume) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 30 | { |
| 31 | u32 gpios; |
| 32 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 33 | printk(BIOS_SPEW, "\n Initializing drive bay...\n"); |
| 34 | gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 |
| 35 | gpios |= (1 << 0); // GPIO33 = ODD |
| 36 | gpios |= (1 << 1); // GPIO34 = IDE_RST# |
| 37 | outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ |
| 38 | |
| 39 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 40 | gpios &= ~(1 << 13); // ?? |
| 41 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 42 | |
| 43 | printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); |
| 44 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 45 | gpios &= ~(1 << 24); // Enable LAN Power |
| 46 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 47 | } |
| 48 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 49 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 50 | void mainboard_lpc_decode(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 51 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 52 | int lpt_en = 0; |
Kyösti Mälkki | bee82ab | 2019-12-26 10:57:43 +0200 | [diff] [blame^] | 53 | u8 val; |
| 54 | |
| 55 | if (get_option(&val, "lpt") == CB_SUCCESS && val) |
| 56 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 57 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 58 | // decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 59 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 60 | // decode range |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 61 | pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 62 | } |
| 63 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 64 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 65 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 66 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 67 | * but safe anyways" method. |
| 68 | */ |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 69 | static void pnp_enter_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 70 | { |
| 71 | unsigned int port = dev >> 8; |
| 72 | outb(0x55, port); |
| 73 | } |
| 74 | |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 75 | static void pnp_exit_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 76 | { |
| 77 | unsigned int port = dev >> 8; |
| 78 | outb(0xaa, port); |
| 79 | } |
| 80 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 81 | void bootblock_mainboard_early_init(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 82 | { |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 83 | pnp_devfn_t dev; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 84 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 85 | dev = PNP_DEV(0x4e, 0x00); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 86 | |
| 87 | pnp_enter_ext_func_mode(dev); |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 88 | pnp_write_config(dev, 0x02, 0x0e); // UART power |
| 89 | pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base |
| 90 | pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base |
| 91 | pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ |
| 92 | pnp_write_config(dev, 0x1e, 1); // no 32khz clock |
| 93 | pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base |
| 94 | pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ |
| 95 | pnp_write_config(dev, 0x2c, 0); // DMA0 FIR |
| 96 | pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 97 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 98 | pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR |
| 99 | pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL |
| 100 | pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR |
| 101 | pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL |
| 102 | pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR |
| 103 | pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL |
| 104 | pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR |
| 105 | pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 106 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 107 | pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT |
| 108 | pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT |
| 109 | pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT |
| 110 | pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR |
| 111 | pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL |
| 112 | pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 |
| 113 | pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 |
| 114 | pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 115 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 116 | pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 |
| 117 | pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 |
| 118 | pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 |
| 119 | pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 |
| 120 | pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 |
| 121 | pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 122 | |
| 123 | pnp_exit_ext_func_mode(dev); |
| 124 | } |
| 125 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 126 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 127 | { |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 128 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 129 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 130 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 131 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 132 | |
| 133 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 134 | RCBA16(D31IR) = 0x0232; |
| 135 | RCBA16(D30IR) = 0x3246; |
| 136 | RCBA16(D29IR) = 0x0237; |
| 137 | RCBA16(D28IR) = 0x3201; |
| 138 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 139 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 140 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 141 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 142 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 143 | /* This should probably go into the ACPI enable trap */ |
| 144 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 145 | RCBA32(0x1e84) = 0x00020001; |
| 146 | RCBA32(0x1e80) = 0x0000fe01; |
| 147 | |
| 148 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 149 | RCBA32(0x1e9c) = 0x000200f0; |
| 150 | RCBA32(0x1e98) = 0x000c0801; |
| 151 | } |