Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 3 | * |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 17 | #include <stdint.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 18 | #include <arch/io.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 19 | #include <cf9_reset.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 20 | #include <delay.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 21 | #include <device/pnp_ops.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 23 | #include <device/pci_def.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 24 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 25 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 26 | #include <console/console.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 27 | #include <arch/romstage.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 28 | #include <northbridge/intel/i945/i945.h> |
| 29 | #include <northbridge/intel/i945/raminit.h> |
| 30 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 31 | #include <southbridge/intel/common/pmclib.h> |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 32 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 33 | |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 34 | static void setup_special_ich7_gpios(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 35 | { |
| 36 | u32 gpios; |
| 37 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 38 | printk(BIOS_SPEW, "\n Initializing drive bay...\n"); |
| 39 | gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 |
| 40 | gpios |= (1 << 0); // GPIO33 = ODD |
| 41 | gpios |= (1 << 1); // GPIO34 = IDE_RST# |
| 42 | outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ |
| 43 | |
| 44 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 45 | gpios &= ~(1 << 13); // ?? |
| 46 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 47 | |
| 48 | printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); |
| 49 | gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level |
| 50 | gpios &= ~(1 << 24); // Enable LAN Power |
| 51 | outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 52 | } |
| 53 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 54 | /* Override the default lpc decode ranges */ |
| 55 | static void mb_lpc_decode(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 56 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 57 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 58 | if (read_option(lpt, 0) != 0) |
| 59 | lpt_en = LPT_LPC_EN; |
| 60 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 61 | // decode range |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 62 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 63 | // decode range |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 64 | pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 65 | } |
| 66 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 67 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 68 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 69 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 70 | * but safe anyways" method. |
| 71 | */ |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 72 | static void pnp_enter_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 73 | { |
| 74 | unsigned int port = dev >> 8; |
| 75 | outb(0x55, port); |
| 76 | } |
| 77 | |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 78 | static void pnp_exit_ext_func_mode(pnp_devfn_t dev) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 79 | { |
| 80 | unsigned int port = dev >> 8; |
| 81 | outb(0xaa, port); |
| 82 | } |
| 83 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 84 | static void early_superio_config(void) |
| 85 | { |
Antonello Dettori | 771d7ec | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 86 | pnp_devfn_t dev; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 87 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 88 | dev = PNP_DEV(0x4e, 0x00); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 89 | |
| 90 | pnp_enter_ext_func_mode(dev); |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 91 | pnp_write_config(dev, 0x02, 0x0e); // UART power |
| 92 | pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base |
| 93 | pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base |
| 94 | pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ |
| 95 | pnp_write_config(dev, 0x1e, 1); // no 32khz clock |
| 96 | pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base |
| 97 | pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ |
| 98 | pnp_write_config(dev, 0x2c, 0); // DMA0 FIR |
| 99 | pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 100 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 101 | pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR |
| 102 | pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL |
| 103 | pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR |
| 104 | pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL |
| 105 | pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR |
| 106 | pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL |
| 107 | pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR |
| 108 | pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 109 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 110 | pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT |
| 111 | pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT |
| 112 | pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT |
| 113 | pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR |
| 114 | pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL |
| 115 | pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 |
| 116 | pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 |
| 117 | pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 118 | |
Elyes HAOUAS | d6c8bdc | 2019-10-11 13:58:29 +0200 | [diff] [blame] | 119 | pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 |
| 120 | pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 |
| 121 | pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 |
| 122 | pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 |
| 123 | pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 |
| 124 | pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 125 | |
| 126 | pnp_exit_ext_func_mode(dev); |
| 127 | } |
| 128 | |
| 129 | static void rcba_config(void) |
| 130 | { |
| 131 | /* Set up virtual channel 0 */ |
| 132 | //RCBA32(0x0014) = 0x80000001; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 133 | |
| 134 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 135 | RCBA32(D31IP) = 0x00042220; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 136 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 137 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 138 | |
| 139 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 140 | RCBA16(D31IR) = 0x0232; |
| 141 | RCBA16(D30IR) = 0x3246; |
| 142 | RCBA16(D29IR) = 0x0237; |
| 143 | RCBA16(D28IR) = 0x3201; |
| 144 | RCBA16(D27IR) = 0x3216; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 145 | |
| 146 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 147 | RCBA8(OIC) = 0x03; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 148 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 149 | /* Disable unused devices */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 150 | RCBA32(FD) |= FD_INTLAN; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 151 | |
| 152 | /* Enable PCIe Root Port Clock Gate */ |
| 153 | // RCBA32(0x341c) = 0x00000001; |
| 154 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 155 | /* This should probably go into the ACPI enable trap */ |
| 156 | /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ |
| 157 | RCBA32(0x1e84) = 0x00020001; |
| 158 | RCBA32(0x1e80) = 0x0000fe01; |
| 159 | |
| 160 | /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ |
| 161 | RCBA32(0x1e9c) = 0x000200f0; |
| 162 | RCBA32(0x1e98) = 0x000c0801; |
| 163 | } |
| 164 | |
| 165 | static void early_ich7_init(void) |
| 166 | { |
| 167 | uint8_t reg8; |
| 168 | uint32_t reg32; |
| 169 | |
| 170 | // program secondary mlt XXX byte? |
Elyes HAOUAS | 6df210b | 2019-10-25 14:05:17 +0200 | [diff] [blame] | 171 | pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 172 | |
| 173 | // reset rtc power status |
Elyes HAOUAS | 6df210b | 2019-10-25 14:05:17 +0200 | [diff] [blame] | 174 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
| 175 | reg8 &= ~RTC_BATTERY_DEAD; |
| 176 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 177 | |
| 178 | // usb transient disconnect |
| 179 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 180 | reg8 |= (3 << 0); |
| 181 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 182 | |
| 183 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 184 | reg32 |= (1 << 29) | (1 << 17); |
| 185 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 186 | |
| 187 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 188 | reg32 |= (1 << 31) | (1 << 27); |
| 189 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 190 | |
Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 191 | ich7_setup_cir(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 192 | } |
| 193 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 194 | void mainboard_romstage_entry(void) |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 195 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 196 | int s3resume = 0; |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 197 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 198 | enable_lapic(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 199 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 200 | i82801gx_lpc_setup(); |
| 201 | mb_lpc_decode(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 202 | early_superio_config(); |
| 203 | |
| 204 | /* Set up the console */ |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 205 | console_init(); |
| 206 | |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 207 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 208 | system_reset(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | /* Perform some early chipset initialization required |
| 212 | * before RAM initialization can work |
| 213 | */ |
| 214 | i945_early_initialization(); |
| 215 | |
Arthur Heymans | 62902ca | 2016-11-29 14:13:43 +0100 | [diff] [blame] | 216 | setup_special_ich7_gpios(); |
| 217 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 218 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 219 | |
| 220 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 221 | enable_smbus(); |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 222 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 223 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 224 | dump_spd_registers(); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 225 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 226 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 227 | |
| 228 | /* Perform some initialization that must run before stage2 */ |
| 229 | early_ich7_init(); |
| 230 | |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 231 | /* This should probably go away. Until now it is required |
| 232 | * and mainboard specific |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 233 | */ |
| 234 | rcba_config(); |
| 235 | |
| 236 | /* Chipset Errata! */ |
| 237 | fixup_i945_errata(); |
| 238 | |
| 239 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 240 | i945_late_initialization(s3resume); |
Stefan Reinauer | 7cfa7f9 | 2010-05-16 14:24:41 +0000 | [diff] [blame] | 241 | } |