Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 7 | #include <device/pci_ids.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
| 9 | #include <intelblocks/gpio.h> |
| 10 | #include <intelblocks/gspi.h> |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 11 | #include <intelblocks/power_limit.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 13 | #include <intelblocks/tcss.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 14 | #include <soc/gpe.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pmc.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <soc/serialio.h> |
| 18 | #include <soc/usb.h> |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 19 | #include <soc/vr_config.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | |
Sumeet Pawnikar | aa49608 | 2021-05-07 20:11:53 +0530 | [diff] [blame] | 22 | /* Types of different SKUs */ |
| 23 | enum soc_intel_alderlake_power_limits { |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 24 | ADL_P_282_CORE, |
| 25 | ADL_P_482_CORE, |
| 26 | ADL_P_682_28W_CORE, |
| 27 | ADL_P_682_45W_CORE, |
Sumeet Pawnikar | 21c431b | 2021-09-30 10:04:41 +0530 | [diff] [blame] | 28 | ADL_M_282_12W_CORE, |
| 29 | ADL_M_282_15W_CORE, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 30 | ADL_M_242_CORE, |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 31 | ADL_P_242_CORE, |
Sumeet Pawnikar | aa49608 | 2021-05-07 20:11:53 +0530 | [diff] [blame] | 32 | ADL_POWER_LIMITS_COUNT |
| 33 | }; |
| 34 | |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 35 | /* TDP values for different SKUs */ |
| 36 | enum soc_intel_alderlake_cpu_tdps { |
| 37 | TDP_9W = 9, |
Sumeet Pawnikar | 21c431b | 2021-09-30 10:04:41 +0530 | [diff] [blame] | 38 | TDP_12W = 12, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 39 | TDP_15W = 15, |
| 40 | TDP_28W = 28, |
| 41 | TDP_45W = 45 |
| 42 | }; |
| 43 | |
| 44 | /* Mapping of different SKUs based on CPU ID and TDP values */ |
| 45 | static const struct { |
| 46 | unsigned int cpu_id; |
| 47 | enum soc_intel_alderlake_power_limits limits; |
| 48 | enum soc_intel_alderlake_cpu_tdps cpu_tdp; |
| 49 | } cpuid_to_adl[] = { |
| 50 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W }, |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 51 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_242_CORE, TDP_15W }, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 52 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, |
| 53 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, |
| 54 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, |
Sumeet Pawnikar | 21c431b | 2021-09-30 10:04:41 +0530 | [diff] [blame] | 55 | { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, |
| 56 | { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 57 | { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, |
| 58 | }; |
| 59 | |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 60 | /* Types of display ports */ |
| 61 | enum ddi_ports { |
| 62 | DDI_PORT_A, |
| 63 | DDI_PORT_B, |
| 64 | DDI_PORT_C, |
| 65 | DDI_PORT_1, |
| 66 | DDI_PORT_2, |
| 67 | DDI_PORT_3, |
| 68 | DDI_PORT_4, |
| 69 | DDI_PORT_COUNT, |
| 70 | }; |
| 71 | |
| 72 | enum ddi_port_flags { |
| 73 | DDI_ENABLE_DDC = 1 << 0, |
| 74 | DDI_ENABLE_HPD = 1 << 1, |
| 75 | }; |
| 76 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 77 | /* |
| 78 | * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2, |
| 79 | * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 |
| 80 | */ |
| 81 | enum fivr_enable_states { |
| 82 | FIVR_ENABLE_S0i1_S0i2 = BIT(0), |
| 83 | FIVR_ENABLE_S0i3 = BIT(1), |
| 84 | FIVR_ENABLE_S3 = BIT(2), |
| 85 | FIVR_ENABLE_S4 = BIT(3), |
| 86 | FIVR_ENABLE_S5 = BIT(4), |
| 87 | }; |
| 88 | |
| 89 | /* |
| 90 | * Enable the following for External V1p05 rail |
| 91 | * BIT0: Retention active switch support |
| 92 | * BIT1: Normal Active voltage supported |
| 93 | * BIT2: Minimum active voltage supported |
| 94 | * BIT3: Minimum Retention voltage supported |
| 95 | */ |
| 96 | enum fivr_voltage_supported { |
| 97 | FIVR_RET_ACTIVE_SWITCH_SUPPORT = BIT(0), |
| 98 | FIVR_VOLTAGE_NORMAL = BIT(1), |
| 99 | FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), |
| 100 | FIVR_VOLTAGE_MIN_RETENTION = BIT(3), |
| 101 | }; |
| 102 | |
| 103 | #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ |
| 104 | FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 105 | /* |
| 106 | * The Max Pkg Cstate |
| 107 | * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, |
| 108 | * 254 - CPU Default , 255 - Auto. |
| 109 | */ |
| 110 | enum pkgcstate_limit { |
| 111 | LIMIT_C0_C1 = 0, |
| 112 | LIMIT_C2 = 1, |
| 113 | LIMIT_C3 = 2, |
| 114 | LIMIT_C6 = 3, |
| 115 | LIMIT_C7 = 4, |
| 116 | LIMIT_C7S = 5, |
| 117 | LIMIT_C8 = 6, |
| 118 | LIMIT_C9 = 7, |
| 119 | LIMIT_C10 = 8, |
| 120 | LIMIT_CPUDEFAULT = 254, |
| 121 | LIMIT_AUTO = 255, |
| 122 | }; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 123 | |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 124 | /* Bit values for use in LpmStateEnableMask. */ |
| 125 | enum lpm_state_mask { |
| 126 | LPM_S0i2_0 = BIT(0), |
| 127 | LPM_S0i2_1 = BIT(1), |
| 128 | LPM_S0i2_2 = BIT(2), |
| 129 | LPM_S0i3_0 = BIT(3), |
| 130 | LPM_S0i3_1 = BIT(4), |
| 131 | LPM_S0i3_2 = BIT(5), |
| 132 | LPM_S0i3_3 = BIT(6), |
| 133 | LPM_S0i3_4 = BIT(7), |
| 134 | LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 |
| 135 | | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, |
| 136 | }; |
| 137 | |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 138 | /* |
| 139 | * FivrSpreadSpectrum: |
| 140 | * Values |
| 141 | * 0 - 0.5%, 3 - 1%, 8 - 1.5%, 18 - 2%, 28 - 3%, 34 - 4%, 39 - 5%, 44 - 6% |
| 142 | */ |
| 143 | enum fivr_spread_spectrum_ratio { |
| 144 | FIVR_SS_0_5 = 0, |
| 145 | FIVR_SS_1 = 3, |
| 146 | FIVR_SS_1_5 = 8, |
| 147 | FIVR_SS_2 = 18, |
| 148 | FIVR_SS_3 = 28, |
| 149 | FIVR_SS_4 = 34, |
| 150 | FIVR_SS_5 = 39, |
| 151 | FIVR_SS_6 = 44, |
| 152 | }; |
| 153 | |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame^] | 154 | /* |
| 155 | * Slew Rate configuration for Deep Package C States for VR domain. |
| 156 | * They are fast time divided by 2. |
| 157 | * 0 - Fast/2 |
| 158 | * 1 - Fast/4 |
| 159 | * 2 - Fast/8 |
| 160 | * 3 - Fast/16 |
| 161 | */ |
| 162 | enum slew_rate { |
| 163 | SLEW_FAST_2, |
| 164 | SLEW_FAST_4, |
| 165 | SLEW_FAST_8, |
| 166 | SLEW_FAST_16 |
| 167 | }; |
| 168 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 169 | struct soc_intel_alderlake_config { |
| 170 | |
| 171 | /* Common struct containing soc config data required by common code */ |
| 172 | struct soc_intel_common_config common_soc_config; |
| 173 | |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 174 | /* Common struct containing power limits configuration information */ |
Sumeet Pawnikar | aa49608 | 2021-05-07 20:11:53 +0530 | [diff] [blame] | 175 | struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT]; |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 176 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 177 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 178 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 179 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 180 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 181 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 182 | |
| 183 | /* Generic IO decode ranges */ |
| 184 | uint32_t gen1_dec; |
| 185 | uint32_t gen2_dec; |
| 186 | uint32_t gen3_dec; |
| 187 | uint32_t gen4_dec; |
| 188 | |
| 189 | /* Enable S0iX support */ |
| 190 | int s0ix_enable; |
| 191 | /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ |
| 192 | uint8_t TcssD3HotDisable; |
| 193 | /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ |
| 194 | uint8_t TcssD3ColdDisable; |
| 195 | /* Enable DPTF support */ |
| 196 | int dptf_enable; |
| 197 | |
| 198 | /* Deep SX enable for both AC and DC */ |
| 199 | int deep_s3_enable_ac; |
| 200 | int deep_s3_enable_dc; |
| 201 | int deep_s5_enable_ac; |
| 202 | int deep_s5_enable_dc; |
| 203 | |
| 204 | /* Deep Sx Configuration |
| 205 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 206 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 207 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 208 | uint32_t deep_sx_config; |
| 209 | |
| 210 | /* TCC activation offset */ |
| 211 | uint32_t tcc_offset; |
| 212 | |
| 213 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 214 | * When enabled memory will be training at two different frequencies. |
| 215 | * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, |
| 216 | * 4:FixedPoint3, 5:Enabled */ |
| 217 | enum { |
| 218 | SaGv_Disabled, |
| 219 | SaGv_FixedPoint0, |
| 220 | SaGv_FixedPoint1, |
| 221 | SaGv_FixedPoint2, |
| 222 | SaGv_FixedPoint3, |
| 223 | SaGv_Enabled, |
| 224 | } SaGv; |
| 225 | |
| 226 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 227 | uint8_t RMT; |
| 228 | |
| 229 | /* USB related */ |
| 230 | struct usb2_port_config usb2_ports[16]; |
| 231 | struct usb3_port_config usb3_ports[10]; |
| 232 | /* Wake Enable Bitmap for USB2 ports */ |
| 233 | uint16_t usb2_wake_enable_bitmap; |
| 234 | /* Wake Enable Bitmap for USB3 ports */ |
| 235 | uint16_t usb3_wake_enable_bitmap; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 236 | /* Program OC pins for TCSS */ |
| 237 | struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 238 | |
| 239 | /* SATA related */ |
| 240 | uint8_t SataEnable; |
| 241 | uint8_t SataMode; |
| 242 | uint8_t SataSalpSupport; |
| 243 | uint8_t SataPortsEnable[8]; |
| 244 | uint8_t SataPortsDevSlp[8]; |
| 245 | |
| 246 | /* |
| 247 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 248 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 249 | */ |
| 250 | uint8_t SataPwrOptimizeDisable; |
| 251 | |
| 252 | /* |
| 253 | * SATA Port Enable Dito Config. |
| 254 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 255 | */ |
| 256 | uint8_t SataPortsEnableDitoConfig[8]; |
| 257 | |
| 258 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 259 | uint8_t SataPortsDmVal[8]; |
| 260 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 261 | uint16_t SataPortsDitoVal[8]; |
| 262 | |
| 263 | /* Audio related */ |
| 264 | uint8_t PchHdaDspEnable; |
Sugnan Prabhu S | 50f8b4e | 2021-03-18 22:08:22 +0530 | [diff] [blame] | 265 | |
| 266 | /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ |
| 267 | enum { |
| 268 | HDA_TMODE_2T = 0, |
| 269 | HDA_TMODE_4T = 2, |
| 270 | HDA_TMODE_8T = 3, |
| 271 | HDA_TMODE_16T = 4, |
| 272 | } PchHdaIDispLinkTmode; |
| 273 | |
| 274 | /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ |
| 275 | enum { |
| 276 | HDA_LINKFREQ_48MHZ = 3, |
| 277 | HDA_LINKFREQ_96MHZ = 4, |
| 278 | } PchHdaIDispLinkFrequency; |
| 279 | |
| 280 | bool PchHdaIDispCodecEnable; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 281 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 282 | struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; |
| 283 | struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; |
| 284 | uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 285 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 286 | /* Gfx related */ |
| 287 | enum { |
| 288 | IGD_SM_0MB = 0x00, |
| 289 | IGD_SM_32MB = 0x01, |
| 290 | IGD_SM_64MB = 0x02, |
| 291 | IGD_SM_96MB = 0x03, |
| 292 | IGD_SM_128MB = 0x04, |
| 293 | IGD_SM_160MB = 0x05, |
| 294 | IGD_SM_4MB = 0xF0, |
| 295 | IGD_SM_8MB = 0xF1, |
| 296 | IGD_SM_12MB = 0xF2, |
| 297 | IGD_SM_16MB = 0xF3, |
| 298 | IGD_SM_20MB = 0xF4, |
| 299 | IGD_SM_24MB = 0xF5, |
| 300 | IGD_SM_28MB = 0xF6, |
| 301 | IGD_SM_36MB = 0xF8, |
| 302 | IGD_SM_40MB = 0xF9, |
| 303 | IGD_SM_44MB = 0xFA, |
| 304 | IGD_SM_48MB = 0xFB, |
| 305 | IGD_SM_52MB = 0xFC, |
| 306 | IGD_SM_56MB = 0xFD, |
| 307 | IGD_SM_60MB = 0xFE, |
| 308 | } IgdDvmt50PreAlloc; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 309 | uint8_t SkipExtGfxScan; |
| 310 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 311 | /* HeciEnabled decides the state of Heci1 at end of boot |
| 312 | * Setting to 0 (default) disables Heci1 and hides the device from OS */ |
| 313 | uint8_t HeciEnabled; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 314 | |
| 315 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 316 | uint8_t eist_enable; |
| 317 | |
| 318 | /* Enable C6 DRAM */ |
| 319 | uint8_t enable_c6dram; |
Michael Niewöhner | d2fadda | 2021-09-27 19:26:20 +0200 | [diff] [blame] | 320 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 321 | /* |
| 322 | * SerialIO device mode selection: |
| 323 | * PchSerialIoDisabled, |
| 324 | * PchSerialIoPci, |
| 325 | * PchSerialIoHidden, |
| 326 | * PchSerialIoLegacyUart, |
| 327 | * PchSerialIoSkipInit |
| 328 | */ |
| 329 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 330 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 331 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 332 | /* |
| 333 | * GSPIn Default Chip Select Mode: |
| 334 | * 0:Hardware Mode, |
| 335 | * 1:Software Mode |
| 336 | */ |
| 337 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 338 | /* |
| 339 | * GSPIn Default Chip Select State: |
| 340 | * 0: Low, |
| 341 | * 1: High |
| 342 | */ |
| 343 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 344 | |
| 345 | /* Debug interface selection */ |
| 346 | enum { |
| 347 | DEBUG_INTERFACE_RAM = (1 << 0), |
| 348 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
| 349 | DEBUG_INTERFACE_USB3 = (1 << 3), |
| 350 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
| 351 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 352 | } debug_interface_flag; |
| 353 | |
| 354 | /* Enable Pch iSCLK */ |
| 355 | uint8_t pch_isclk; |
| 356 | |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 357 | /* CNVi BT Core Enable/Disable */ |
| 358 | bool CnviBtCore; |
| 359 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 360 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 361 | bool CnviBtAudioOffload; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 362 | |
| 363 | /* |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 364 | * These GPIOs will be programmed by the IOM to handle biasing of the |
| 365 | * Type-C aux (SBU) signals when certain alternate modes are used. |
| 366 | * `pad_auxn_dc` should be assigned to the GPIO pad providing negative |
| 367 | * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, |
| 368 | * `pad_auxp_dc` should be assigned to the GPIO providing positive bias |
| 369 | * (name often contains `AUXP_DC` or `_AUX_P`). |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 370 | */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 371 | struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 372 | |
| 373 | /* |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 374 | * SOC Aux orientation override: |
| 375 | * This is a bitfield that corresponds to up to 4 TCSS ports on ADL. |
| 376 | * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. |
| 377 | * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines |
| 378 | * on the motherboard. |
| 379 | */ |
| 380 | uint16_t TcssAuxOri; |
| 381 | |
| 382 | /* Connect Topology Command timeout value */ |
| 383 | uint16_t ITbtConnectTopologyTimeoutInMs; |
| 384 | |
| 385 | /* |
| 386 | * Override GPIO PM configuration: |
| 387 | * 0: Use FSP default GPIO PM program, |
| 388 | * 1: coreboot to override GPIO PM program |
| 389 | */ |
| 390 | uint8_t gpio_override_pm; |
| 391 | |
| 392 | /* |
| 393 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 394 | * Bit 6-7: Reserved |
| 395 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 396 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 397 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 398 | * Bit 2: MISCCFG_GSXLCGEN |
| 399 | * Bit 1: MISCCFG_GPDPCGEN |
| 400 | * Bit 0: MISCCFG_GPDLCGEN |
| 401 | */ |
| 402 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 403 | |
| 404 | /* DP config */ |
| 405 | /* |
| 406 | * Port config |
| 407 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 408 | */ |
| 409 | uint8_t DdiPortAConfig; |
| 410 | uint8_t DdiPortBConfig; |
| 411 | |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 412 | /* Enable(1)/Disable(0) HPD/DDC */ |
| 413 | uint8_t ddi_ports_config[DDI_PORT_COUNT]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 414 | |
| 415 | /* Hybrid storage mode enable (1) / disable (0) |
| 416 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 417 | * accordingly */ |
| 418 | uint8_t HybridStorageMode; |
| 419 | |
| 420 | /* |
| 421 | * Override CPU flex ratio value: |
| 422 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 423 | * Valid Range 0 to 63. |
| 424 | * |
| 425 | * In general descriptor provides option to set default cpu flex ratio. |
| 426 | * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. |
| 427 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 428 | * |
| 429 | * Only override CPU flex ratio if don't want to boot with non-turbo max. |
| 430 | */ |
| 431 | uint8_t cpu_ratio_override; |
| 432 | |
| 433 | /* |
| 434 | * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. |
| 435 | * Default 0. Setting this to 1 disables the DMI Power Optimizer. |
| 436 | */ |
| 437 | uint8_t DmiPwrOptimizeDisable; |
| 438 | |
| 439 | /* |
| 440 | * Enable(1)/Disable(0) CPU Replacement check. |
| 441 | * Default 0. Setting this to 1 to check CPU replacement. |
| 442 | */ |
| 443 | uint8_t CpuReplacementCheck; |
| 444 | |
| 445 | /* ISA Serial Base selection. */ |
| 446 | enum { |
| 447 | ISA_SERIAL_BASE_ADDR_3F8, |
| 448 | ISA_SERIAL_BASE_ADDR_2F8, |
| 449 | } IsaSerialUartBase; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 450 | |
| 451 | /* structure containing various settings for PCH FIVRs */ |
| 452 | struct { |
| 453 | bool configure_ext_fivr; |
| 454 | enum fivr_enable_states v1p05_enable_bitmap; |
| 455 | enum fivr_enable_states vnn_enable_bitmap; |
| 456 | enum fivr_enable_states vnn_sx_enable_bitmap; |
| 457 | enum fivr_voltage_supported v1p05_supported_voltage_bitmap; |
| 458 | enum fivr_voltage_supported vnn_supported_voltage_bitmap; |
| 459 | /* V1p05 Rail Voltage in mv */ |
| 460 | int v1p05_voltage_mv; |
| 461 | /* Vnn Rail Voltage in mv */ |
| 462 | int vnn_voltage_mv; |
| 463 | /* VnnSx Rail Voltage in mv */ |
| 464 | int vnn_sx_voltage_mv; |
| 465 | /* External Icc Max for V1p05 rail in mA */ |
| 466 | int v1p05_icc_max_ma; |
| 467 | /* External Icc Max for VnnSx rail in mA */ |
| 468 | int vnn_icc_max_ma; |
| 469 | } ext_fivr_settings; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 470 | |
| 471 | /* VrConfig Settings. |
| 472 | * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT. |
| 473 | */ |
| 474 | struct vr_config domain_vr_config[NUM_VR_DOMAINS]; |
Casper Chang | 8fcefd3 | 2021-09-22 22:35:54 -0400 | [diff] [blame] | 475 | |
| 476 | uint16_t MaxDramSpeed; |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 477 | |
| 478 | enum { |
| 479 | SLP_S3_ASSERTION_DEFAULT, |
| 480 | SLP_S3_ASSERTION_60_US, |
| 481 | SLP_S3_ASSERTION_1_MS, |
| 482 | SLP_S3_ASSERTION_50_MS, |
| 483 | SLP_S3_ASSERTION_2_S, |
| 484 | } pch_slp_s3_min_assertion_width; |
| 485 | |
| 486 | enum { |
| 487 | SLP_S4_ASSERTION_DEFAULT, |
| 488 | SLP_S4_ASSERTION_1S, |
| 489 | SLP_S4_ASSERTION_2S, |
| 490 | SLP_S4_ASSERTION_3S, |
| 491 | SLP_S4_ASSERTION_4S, |
| 492 | } pch_slp_s4_min_assertion_width; |
| 493 | |
| 494 | enum { |
| 495 | SLP_SUS_ASSERTION_DEFAULT, |
| 496 | SLP_SUS_ASSERTION_0_MS, |
| 497 | SLP_SUS_ASSERTION_500_MS, |
| 498 | SLP_SUS_ASSERTION_1_S, |
| 499 | SLP_SUS_ASSERTION_4_S, |
| 500 | } pch_slp_sus_min_assertion_width; |
| 501 | |
| 502 | enum { |
| 503 | SLP_A_ASSERTION_DEFAULT, |
| 504 | SLP_A_ASSERTION_0_MS, |
| 505 | SLP_A_ASSERTION_4_S, |
| 506 | SLP_A_ASSERTION_98_MS, |
| 507 | SLP_A_ASSERTION_2_S, |
| 508 | } pch_slp_a_min_assertion_width; |
| 509 | |
| 510 | /* |
| 511 | * PCH PM Reset Power Cycle Duration |
| 512 | * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the |
| 513 | * stretch duration programmed in the following registers: |
| 514 | * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 515 | * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 516 | * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 517 | * - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 518 | */ |
| 519 | enum { |
| 520 | POWER_CYCLE_DURATION_DEFAULT, |
| 521 | POWER_CYCLE_DURATION_1S, |
| 522 | POWER_CYCLE_DURATION_2S, |
| 523 | POWER_CYCLE_DURATION_3S, |
| 524 | POWER_CYCLE_DURATION_4S, |
| 525 | } pch_reset_power_cycle_duration; |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 526 | |
| 527 | /* Platform Power Pmax */ |
| 528 | uint16_t PsysPmax; |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 529 | /* |
| 530 | * FivrRfiFrequency |
| 531 | * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. |
| 532 | * 0: Auto |
| 533 | * Range varies based on XTAL clock: |
| 534 | * 0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock |
| 535 | * 0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock |
| 536 | */ |
| 537 | uint32_t FivrRfiFrequency; |
| 538 | /* |
| 539 | * FivrSpreadSpectrum |
| 540 | * Set the Spread Spectrum Range. |
| 541 | * Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. |
| 542 | * Each Range is translated to an encoded value for FIVR register. |
| 543 | * 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. |
| 544 | */ |
| 545 | uint8_t FivrSpreadSpectrum; |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame^] | 546 | /* Enable or Disable Acoustic Noise Mitigation feature */ |
| 547 | uint8_t AcousticNoiseMitigation; |
| 548 | /* Disable Fast Slew Rate for Deep Package C States for VR domains */ |
| 549 | uint8_t FastPkgCRampDisable[NUM_VR_DOMAINS]; |
| 550 | /* |
| 551 | * Slew Rate configuration for Deep Package C States for VR domains |
| 552 | * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values |
| 553 | */ |
| 554 | uint8_t SlowSlewRate[NUM_VR_DOMAINS]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 555 | }; |
| 556 | |
| 557 | typedef struct soc_intel_alderlake_config config_t; |
| 558 | |
| 559 | #endif |