soc/intel/alderlake: add MaxDramSpeed config
This change add MaxDramSpeed for variants usage to config dram speed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 5f556c8..b9be02b 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -436,6 +436,8 @@
* 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT.
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
+
+ uint16_t MaxDramSpeed;
};
typedef struct soc_intel_alderlake_config config_t;