Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 7 | #include <device/pci_ids.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
| 9 | #include <intelblocks/gpio.h> |
| 10 | #include <intelblocks/gspi.h> |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 11 | #include <intelblocks/power_limit.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 13 | #include <intelblocks/tcss.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 14 | #include <soc/gpe.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pmc.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <soc/serialio.h> |
| 18 | #include <soc/usb.h> |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 19 | #include <soc/vr_config.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 20 | #include <stdint.h> |
| 21 | |
Sumeet Pawnikar | aa49608 | 2021-05-07 20:11:53 +0530 | [diff] [blame] | 22 | /* Types of different SKUs */ |
| 23 | enum soc_intel_alderlake_power_limits { |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 24 | ADL_P_282_CORE, |
| 25 | ADL_P_482_CORE, |
| 26 | ADL_P_682_28W_CORE, |
| 27 | ADL_P_682_45W_CORE, |
Sumeet Pawnikar | 21c431b | 2021-09-30 10:04:41 +0530 | [diff] [blame] | 28 | ADL_M_282_12W_CORE, |
| 29 | ADL_M_282_15W_CORE, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 30 | ADL_M_242_CORE, |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 31 | ADL_P_242_CORE, |
Sumeet Pawnikar | aa49608 | 2021-05-07 20:11:53 +0530 | [diff] [blame] | 32 | ADL_POWER_LIMITS_COUNT |
| 33 | }; |
| 34 | |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 35 | /* TDP values for different SKUs */ |
| 36 | enum soc_intel_alderlake_cpu_tdps { |
| 37 | TDP_9W = 9, |
Sumeet Pawnikar | 21c431b | 2021-09-30 10:04:41 +0530 | [diff] [blame] | 38 | TDP_12W = 12, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 39 | TDP_15W = 15, |
| 40 | TDP_28W = 28, |
| 41 | TDP_45W = 45 |
| 42 | }; |
| 43 | |
| 44 | /* Mapping of different SKUs based on CPU ID and TDP values */ |
| 45 | static const struct { |
| 46 | unsigned int cpu_id; |
| 47 | enum soc_intel_alderlake_power_limits limits; |
| 48 | enum soc_intel_alderlake_cpu_tdps cpu_tdp; |
| 49 | } cpuid_to_adl[] = { |
| 50 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, ADL_P_282_CORE, TDP_15W }, |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 51 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, ADL_P_242_CORE, TDP_15W }, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 52 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, ADL_P_482_CORE, TDP_28W }, |
| 53 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, |
| 54 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, ADL_P_682_45W_CORE, TDP_45W }, |
Sumeet Pawnikar | 21c431b | 2021-09-30 10:04:41 +0530 | [diff] [blame] | 55 | { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, |
| 56 | { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, |
Sumeet Pawnikar | eaf87a9 | 2021-08-31 17:01:02 +0530 | [diff] [blame] | 57 | { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, |
| 58 | }; |
| 59 | |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 60 | /* Types of display ports */ |
| 61 | enum ddi_ports { |
| 62 | DDI_PORT_A, |
| 63 | DDI_PORT_B, |
| 64 | DDI_PORT_C, |
| 65 | DDI_PORT_1, |
| 66 | DDI_PORT_2, |
| 67 | DDI_PORT_3, |
| 68 | DDI_PORT_4, |
| 69 | DDI_PORT_COUNT, |
| 70 | }; |
| 71 | |
| 72 | enum ddi_port_flags { |
| 73 | DDI_ENABLE_DDC = 1 << 0, |
| 74 | DDI_ENABLE_HPD = 1 << 1, |
| 75 | }; |
| 76 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 77 | /* |
| 78 | * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2, |
| 79 | * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 |
| 80 | */ |
| 81 | enum fivr_enable_states { |
| 82 | FIVR_ENABLE_S0i1_S0i2 = BIT(0), |
| 83 | FIVR_ENABLE_S0i3 = BIT(1), |
| 84 | FIVR_ENABLE_S3 = BIT(2), |
| 85 | FIVR_ENABLE_S4 = BIT(3), |
| 86 | FIVR_ENABLE_S5 = BIT(4), |
| 87 | }; |
| 88 | |
| 89 | /* |
| 90 | * Enable the following for External V1p05 rail |
| 91 | * BIT0: Retention active switch support |
| 92 | * BIT1: Normal Active voltage supported |
| 93 | * BIT2: Minimum active voltage supported |
| 94 | * BIT3: Minimum Retention voltage supported |
| 95 | */ |
| 96 | enum fivr_voltage_supported { |
| 97 | FIVR_RET_ACTIVE_SWITCH_SUPPORT = BIT(0), |
| 98 | FIVR_VOLTAGE_NORMAL = BIT(1), |
| 99 | FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), |
| 100 | FIVR_VOLTAGE_MIN_RETENTION = BIT(3), |
| 101 | }; |
| 102 | |
| 103 | #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ |
| 104 | FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 105 | /* |
| 106 | * The Max Pkg Cstate |
| 107 | * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, |
| 108 | * 254 - CPU Default , 255 - Auto. |
| 109 | */ |
| 110 | enum pkgcstate_limit { |
| 111 | LIMIT_C0_C1 = 0, |
| 112 | LIMIT_C2 = 1, |
| 113 | LIMIT_C3 = 2, |
| 114 | LIMIT_C6 = 3, |
| 115 | LIMIT_C7 = 4, |
| 116 | LIMIT_C7S = 5, |
| 117 | LIMIT_C8 = 6, |
| 118 | LIMIT_C9 = 7, |
| 119 | LIMIT_C10 = 8, |
| 120 | LIMIT_CPUDEFAULT = 254, |
| 121 | LIMIT_AUTO = 255, |
| 122 | }; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 123 | |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 124 | /* Bit values for use in LpmStateEnableMask. */ |
| 125 | enum lpm_state_mask { |
| 126 | LPM_S0i2_0 = BIT(0), |
| 127 | LPM_S0i2_1 = BIT(1), |
| 128 | LPM_S0i2_2 = BIT(2), |
| 129 | LPM_S0i3_0 = BIT(3), |
| 130 | LPM_S0i3_1 = BIT(4), |
| 131 | LPM_S0i3_2 = BIT(5), |
| 132 | LPM_S0i3_3 = BIT(6), |
| 133 | LPM_S0i3_4 = BIT(7), |
| 134 | LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 |
| 135 | | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, |
| 136 | }; |
| 137 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 138 | struct soc_intel_alderlake_config { |
| 139 | |
| 140 | /* Common struct containing soc config data required by common code */ |
| 141 | struct soc_intel_common_config common_soc_config; |
| 142 | |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 143 | /* Common struct containing power limits configuration information */ |
Sumeet Pawnikar | aa49608 | 2021-05-07 20:11:53 +0530 | [diff] [blame] | 144 | struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT]; |
Sumeet R Pawnikar | 77298c6 | 2021-03-10 21:09:37 +0530 | [diff] [blame] | 145 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 146 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 147 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 148 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 149 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 150 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 151 | |
| 152 | /* Generic IO decode ranges */ |
| 153 | uint32_t gen1_dec; |
| 154 | uint32_t gen2_dec; |
| 155 | uint32_t gen3_dec; |
| 156 | uint32_t gen4_dec; |
| 157 | |
| 158 | /* Enable S0iX support */ |
| 159 | int s0ix_enable; |
| 160 | /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ |
| 161 | uint8_t TcssD3HotDisable; |
| 162 | /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ |
| 163 | uint8_t TcssD3ColdDisable; |
| 164 | /* Enable DPTF support */ |
| 165 | int dptf_enable; |
| 166 | |
| 167 | /* Deep SX enable for both AC and DC */ |
| 168 | int deep_s3_enable_ac; |
| 169 | int deep_s3_enable_dc; |
| 170 | int deep_s5_enable_ac; |
| 171 | int deep_s5_enable_dc; |
| 172 | |
| 173 | /* Deep Sx Configuration |
| 174 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 175 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 176 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 177 | uint32_t deep_sx_config; |
| 178 | |
| 179 | /* TCC activation offset */ |
| 180 | uint32_t tcc_offset; |
| 181 | |
| 182 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 183 | * When enabled memory will be training at two different frequencies. |
| 184 | * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, |
| 185 | * 4:FixedPoint3, 5:Enabled */ |
| 186 | enum { |
| 187 | SaGv_Disabled, |
| 188 | SaGv_FixedPoint0, |
| 189 | SaGv_FixedPoint1, |
| 190 | SaGv_FixedPoint2, |
| 191 | SaGv_FixedPoint3, |
| 192 | SaGv_Enabled, |
| 193 | } SaGv; |
| 194 | |
| 195 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 196 | uint8_t RMT; |
| 197 | |
| 198 | /* USB related */ |
| 199 | struct usb2_port_config usb2_ports[16]; |
| 200 | struct usb3_port_config usb3_ports[10]; |
| 201 | /* Wake Enable Bitmap for USB2 ports */ |
| 202 | uint16_t usb2_wake_enable_bitmap; |
| 203 | /* Wake Enable Bitmap for USB3 ports */ |
| 204 | uint16_t usb3_wake_enable_bitmap; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 205 | /* Program OC pins for TCSS */ |
| 206 | struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 207 | |
| 208 | /* SATA related */ |
| 209 | uint8_t SataEnable; |
| 210 | uint8_t SataMode; |
| 211 | uint8_t SataSalpSupport; |
| 212 | uint8_t SataPortsEnable[8]; |
| 213 | uint8_t SataPortsDevSlp[8]; |
| 214 | |
| 215 | /* |
| 216 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 217 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 218 | */ |
| 219 | uint8_t SataPwrOptimizeDisable; |
| 220 | |
| 221 | /* |
| 222 | * SATA Port Enable Dito Config. |
| 223 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 224 | */ |
| 225 | uint8_t SataPortsEnableDitoConfig[8]; |
| 226 | |
| 227 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 228 | uint8_t SataPortsDmVal[8]; |
| 229 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 230 | uint16_t SataPortsDitoVal[8]; |
| 231 | |
| 232 | /* Audio related */ |
| 233 | uint8_t PchHdaDspEnable; |
Sugnan Prabhu S | 50f8b4e | 2021-03-18 22:08:22 +0530 | [diff] [blame] | 234 | |
| 235 | /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */ |
| 236 | enum { |
| 237 | HDA_TMODE_2T = 0, |
| 238 | HDA_TMODE_4T = 2, |
| 239 | HDA_TMODE_8T = 3, |
| 240 | HDA_TMODE_16T = 4, |
| 241 | } PchHdaIDispLinkTmode; |
| 242 | |
| 243 | /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */ |
| 244 | enum { |
| 245 | HDA_LINKFREQ_48MHZ = 3, |
| 246 | HDA_LINKFREQ_96MHZ = 4, |
| 247 | } PchHdaIDispLinkFrequency; |
| 248 | |
| 249 | bool PchHdaIDispCodecEnable; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 250 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 251 | struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; |
| 252 | struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; |
| 253 | uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 254 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 255 | /* Gfx related */ |
| 256 | enum { |
| 257 | IGD_SM_0MB = 0x00, |
| 258 | IGD_SM_32MB = 0x01, |
| 259 | IGD_SM_64MB = 0x02, |
| 260 | IGD_SM_96MB = 0x03, |
| 261 | IGD_SM_128MB = 0x04, |
| 262 | IGD_SM_160MB = 0x05, |
| 263 | IGD_SM_4MB = 0xF0, |
| 264 | IGD_SM_8MB = 0xF1, |
| 265 | IGD_SM_12MB = 0xF2, |
| 266 | IGD_SM_16MB = 0xF3, |
| 267 | IGD_SM_20MB = 0xF4, |
| 268 | IGD_SM_24MB = 0xF5, |
| 269 | IGD_SM_28MB = 0xF6, |
| 270 | IGD_SM_36MB = 0xF8, |
| 271 | IGD_SM_40MB = 0xF9, |
| 272 | IGD_SM_44MB = 0xFA, |
| 273 | IGD_SM_48MB = 0xFB, |
| 274 | IGD_SM_52MB = 0xFC, |
| 275 | IGD_SM_56MB = 0xFD, |
| 276 | IGD_SM_60MB = 0xFE, |
| 277 | } IgdDvmt50PreAlloc; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 278 | uint8_t SkipExtGfxScan; |
| 279 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 280 | /* HeciEnabled decides the state of Heci1 at end of boot |
| 281 | * Setting to 0 (default) disables Heci1 and hides the device from OS */ |
| 282 | uint8_t HeciEnabled; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 283 | |
| 284 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 285 | uint8_t eist_enable; |
| 286 | |
| 287 | /* Enable C6 DRAM */ |
| 288 | uint8_t enable_c6dram; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 289 | uint8_t PmTimerDisabled; |
| 290 | /* |
| 291 | * SerialIO device mode selection: |
| 292 | * PchSerialIoDisabled, |
| 293 | * PchSerialIoPci, |
| 294 | * PchSerialIoHidden, |
| 295 | * PchSerialIoLegacyUart, |
| 296 | * PchSerialIoSkipInit |
| 297 | */ |
| 298 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 299 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 300 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 301 | /* |
| 302 | * GSPIn Default Chip Select Mode: |
| 303 | * 0:Hardware Mode, |
| 304 | * 1:Software Mode |
| 305 | */ |
| 306 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 307 | /* |
| 308 | * GSPIn Default Chip Select State: |
| 309 | * 0: Low, |
| 310 | * 1: High |
| 311 | */ |
| 312 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 313 | |
| 314 | /* Debug interface selection */ |
| 315 | enum { |
| 316 | DEBUG_INTERFACE_RAM = (1 << 0), |
| 317 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
| 318 | DEBUG_INTERFACE_USB3 = (1 << 3), |
| 319 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
| 320 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 321 | } debug_interface_flag; |
| 322 | |
| 323 | /* Enable Pch iSCLK */ |
| 324 | uint8_t pch_isclk; |
| 325 | |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 326 | /* CNVi BT Core Enable/Disable */ |
| 327 | bool CnviBtCore; |
| 328 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 329 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 330 | bool CnviBtAudioOffload; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 331 | |
| 332 | /* |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 333 | * These GPIOs will be programmed by the IOM to handle biasing of the |
| 334 | * Type-C aux (SBU) signals when certain alternate modes are used. |
| 335 | * `pad_auxn_dc` should be assigned to the GPIO pad providing negative |
| 336 | * bias (name usually contains `AUXN_DC` or `AUX_N`); similarly, |
| 337 | * `pad_auxp_dc` should be assigned to the GPIO providing positive bias |
| 338 | * (name often contains `AUXP_DC` or `_AUX_P`). |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 339 | */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 340 | struct typec_aux_bias_pads typec_aux_bias_pads[MAX_TYPE_C_PORTS]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 341 | |
| 342 | /* |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 343 | * SOC Aux orientation override: |
| 344 | * This is a bitfield that corresponds to up to 4 TCSS ports on ADL. |
| 345 | * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. |
| 346 | * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines |
| 347 | * on the motherboard. |
| 348 | */ |
| 349 | uint16_t TcssAuxOri; |
| 350 | |
| 351 | /* Connect Topology Command timeout value */ |
| 352 | uint16_t ITbtConnectTopologyTimeoutInMs; |
| 353 | |
| 354 | /* |
| 355 | * Override GPIO PM configuration: |
| 356 | * 0: Use FSP default GPIO PM program, |
| 357 | * 1: coreboot to override GPIO PM program |
| 358 | */ |
| 359 | uint8_t gpio_override_pm; |
| 360 | |
| 361 | /* |
| 362 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 363 | * Bit 6-7: Reserved |
| 364 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 365 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 366 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 367 | * Bit 2: MISCCFG_GSXLCGEN |
| 368 | * Bit 1: MISCCFG_GPDPCGEN |
| 369 | * Bit 0: MISCCFG_GPDLCGEN |
| 370 | */ |
| 371 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 372 | |
| 373 | /* DP config */ |
| 374 | /* |
| 375 | * Port config |
| 376 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 377 | */ |
| 378 | uint8_t DdiPortAConfig; |
| 379 | uint8_t DdiPortBConfig; |
| 380 | |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 381 | /* Enable(1)/Disable(0) HPD/DDC */ |
| 382 | uint8_t ddi_ports_config[DDI_PORT_COUNT]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 383 | |
| 384 | /* Hybrid storage mode enable (1) / disable (0) |
| 385 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 386 | * accordingly */ |
| 387 | uint8_t HybridStorageMode; |
| 388 | |
| 389 | /* |
| 390 | * Override CPU flex ratio value: |
| 391 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 392 | * Valid Range 0 to 63. |
| 393 | * |
| 394 | * In general descriptor provides option to set default cpu flex ratio. |
| 395 | * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. |
| 396 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 397 | * |
| 398 | * Only override CPU flex ratio if don't want to boot with non-turbo max. |
| 399 | */ |
| 400 | uint8_t cpu_ratio_override; |
| 401 | |
| 402 | /* |
| 403 | * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. |
| 404 | * Default 0. Setting this to 1 disables the DMI Power Optimizer. |
| 405 | */ |
| 406 | uint8_t DmiPwrOptimizeDisable; |
| 407 | |
| 408 | /* |
| 409 | * Enable(1)/Disable(0) CPU Replacement check. |
| 410 | * Default 0. Setting this to 1 to check CPU replacement. |
| 411 | */ |
| 412 | uint8_t CpuReplacementCheck; |
| 413 | |
| 414 | /* ISA Serial Base selection. */ |
| 415 | enum { |
| 416 | ISA_SERIAL_BASE_ADDR_3F8, |
| 417 | ISA_SERIAL_BASE_ADDR_2F8, |
| 418 | } IsaSerialUartBase; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 419 | |
| 420 | /* structure containing various settings for PCH FIVRs */ |
| 421 | struct { |
| 422 | bool configure_ext_fivr; |
| 423 | enum fivr_enable_states v1p05_enable_bitmap; |
| 424 | enum fivr_enable_states vnn_enable_bitmap; |
| 425 | enum fivr_enable_states vnn_sx_enable_bitmap; |
| 426 | enum fivr_voltage_supported v1p05_supported_voltage_bitmap; |
| 427 | enum fivr_voltage_supported vnn_supported_voltage_bitmap; |
| 428 | /* V1p05 Rail Voltage in mv */ |
| 429 | int v1p05_voltage_mv; |
| 430 | /* Vnn Rail Voltage in mv */ |
| 431 | int vnn_voltage_mv; |
| 432 | /* VnnSx Rail Voltage in mv */ |
| 433 | int vnn_sx_voltage_mv; |
| 434 | /* External Icc Max for V1p05 rail in mA */ |
| 435 | int v1p05_icc_max_ma; |
| 436 | /* External Icc Max for VnnSx rail in mA */ |
| 437 | int vnn_icc_max_ma; |
| 438 | } ext_fivr_settings; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 439 | |
| 440 | /* VrConfig Settings. |
| 441 | * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT. |
| 442 | */ |
| 443 | struct vr_config domain_vr_config[NUM_VR_DOMAINS]; |
Casper Chang | 8fcefd3 | 2021-09-22 22:35:54 -0400 | [diff] [blame] | 444 | |
| 445 | uint16_t MaxDramSpeed; |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 446 | |
| 447 | enum { |
| 448 | SLP_S3_ASSERTION_DEFAULT, |
| 449 | SLP_S3_ASSERTION_60_US, |
| 450 | SLP_S3_ASSERTION_1_MS, |
| 451 | SLP_S3_ASSERTION_50_MS, |
| 452 | SLP_S3_ASSERTION_2_S, |
| 453 | } pch_slp_s3_min_assertion_width; |
| 454 | |
| 455 | enum { |
| 456 | SLP_S4_ASSERTION_DEFAULT, |
| 457 | SLP_S4_ASSERTION_1S, |
| 458 | SLP_S4_ASSERTION_2S, |
| 459 | SLP_S4_ASSERTION_3S, |
| 460 | SLP_S4_ASSERTION_4S, |
| 461 | } pch_slp_s4_min_assertion_width; |
| 462 | |
| 463 | enum { |
| 464 | SLP_SUS_ASSERTION_DEFAULT, |
| 465 | SLP_SUS_ASSERTION_0_MS, |
| 466 | SLP_SUS_ASSERTION_500_MS, |
| 467 | SLP_SUS_ASSERTION_1_S, |
| 468 | SLP_SUS_ASSERTION_4_S, |
| 469 | } pch_slp_sus_min_assertion_width; |
| 470 | |
| 471 | enum { |
| 472 | SLP_A_ASSERTION_DEFAULT, |
| 473 | SLP_A_ASSERTION_0_MS, |
| 474 | SLP_A_ASSERTION_4_S, |
| 475 | SLP_A_ASSERTION_98_MS, |
| 476 | SLP_A_ASSERTION_2_S, |
| 477 | } pch_slp_a_min_assertion_width; |
| 478 | |
| 479 | /* |
| 480 | * PCH PM Reset Power Cycle Duration |
| 481 | * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the |
| 482 | * stretch duration programmed in the following registers: |
| 483 | * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 484 | * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 485 | * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 486 | * - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 487 | */ |
| 488 | enum { |
| 489 | POWER_CYCLE_DURATION_DEFAULT, |
| 490 | POWER_CYCLE_DURATION_1S, |
| 491 | POWER_CYCLE_DURATION_2S, |
| 492 | POWER_CYCLE_DURATION_3S, |
| 493 | POWER_CYCLE_DURATION_4S, |
| 494 | } pch_reset_power_cycle_duration; |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame^] | 495 | |
| 496 | /* Platform Power Pmax */ |
| 497 | uint16_t PsysPmax; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 498 | }; |
| 499 | |
| 500 | typedef struct soc_intel_alderlake_config config_t; |
| 501 | |
| 502 | #endif |