soc/intel/alderlake: Add support for power cycle and SLP signal duration
The UPDs for PM power cycle duration and SLP_* signal durations are all
identical to Tiger Lake, so add similar support, but use enums instead
of comments to represent the durations symbolically.
BUG=b:184799383
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a531f042658894bcbc6a76eff453c06e90d66b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57891
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index b9be02b..47f6d59 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -438,6 +438,55 @@
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
uint16_t MaxDramSpeed;
+
+ enum {
+ SLP_S3_ASSERTION_DEFAULT,
+ SLP_S3_ASSERTION_60_US,
+ SLP_S3_ASSERTION_1_MS,
+ SLP_S3_ASSERTION_50_MS,
+ SLP_S3_ASSERTION_2_S,
+ } pch_slp_s3_min_assertion_width;
+
+ enum {
+ SLP_S4_ASSERTION_DEFAULT,
+ SLP_S4_ASSERTION_1S,
+ SLP_S4_ASSERTION_2S,
+ SLP_S4_ASSERTION_3S,
+ SLP_S4_ASSERTION_4S,
+ } pch_slp_s4_min_assertion_width;
+
+ enum {
+ SLP_SUS_ASSERTION_DEFAULT,
+ SLP_SUS_ASSERTION_0_MS,
+ SLP_SUS_ASSERTION_500_MS,
+ SLP_SUS_ASSERTION_1_S,
+ SLP_SUS_ASSERTION_4_S,
+ } pch_slp_sus_min_assertion_width;
+
+ enum {
+ SLP_A_ASSERTION_DEFAULT,
+ SLP_A_ASSERTION_0_MS,
+ SLP_A_ASSERTION_4_S,
+ SLP_A_ASSERTION_98_MS,
+ SLP_A_ASSERTION_2_S,
+ } pch_slp_a_min_assertion_width;
+
+ /*
+ * PCH PM Reset Power Cycle Duration
+ * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
+ * stretch duration programmed in the following registers:
+ * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+ * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+ * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+ */
+ enum {
+ POWER_CYCLE_DURATION_DEFAULT,
+ POWER_CYCLE_DURATION_1S,
+ POWER_CYCLE_DURATION_2S,
+ POWER_CYCLE_DURATION_3S,
+ POWER_CYCLE_DURATION_4S,
+ } pch_reset_power_cycle_duration;
};
typedef struct soc_intel_alderlake_config config_t;