Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
| 7 | #include <intelblocks/cfg.h> |
| 8 | #include <intelblocks/gpio.h> |
| 9 | #include <intelblocks/gspi.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 10 | #include <intelblocks/pcie_rp.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 11 | #include <soc/gpe.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 12 | #include <soc/pci_devs.h> |
| 13 | #include <soc/pmc.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 14 | #include <soc/serialio.h> |
| 15 | #include <soc/usb.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 16 | #include <stdint.h> |
| 17 | |
| 18 | #define MAX_HD_AUDIO_DMIC_LINKS 2 |
| 19 | #define MAX_HD_AUDIO_SNDW_LINKS 4 |
| 20 | #define MAX_HD_AUDIO_SSP_LINKS 6 |
| 21 | |
| 22 | struct soc_intel_alderlake_config { |
| 23 | |
| 24 | /* Common struct containing soc config data required by common code */ |
| 25 | struct soc_intel_common_config common_soc_config; |
| 26 | |
| 27 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 28 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 29 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 30 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 31 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 32 | |
| 33 | /* Generic IO decode ranges */ |
| 34 | uint32_t gen1_dec; |
| 35 | uint32_t gen2_dec; |
| 36 | uint32_t gen3_dec; |
| 37 | uint32_t gen4_dec; |
| 38 | |
| 39 | /* Enable S0iX support */ |
| 40 | int s0ix_enable; |
| 41 | /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ |
| 42 | uint8_t TcssD3HotDisable; |
| 43 | /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ |
| 44 | uint8_t TcssD3ColdDisable; |
| 45 | /* Enable DPTF support */ |
| 46 | int dptf_enable; |
| 47 | |
| 48 | /* Deep SX enable for both AC and DC */ |
| 49 | int deep_s3_enable_ac; |
| 50 | int deep_s3_enable_dc; |
| 51 | int deep_s5_enable_ac; |
| 52 | int deep_s5_enable_dc; |
| 53 | |
| 54 | /* Deep Sx Configuration |
| 55 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 56 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 57 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 58 | uint32_t deep_sx_config; |
| 59 | |
| 60 | /* TCC activation offset */ |
| 61 | uint32_t tcc_offset; |
| 62 | |
| 63 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 64 | * When enabled memory will be training at two different frequencies. |
| 65 | * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, |
| 66 | * 4:FixedPoint3, 5:Enabled */ |
| 67 | enum { |
| 68 | SaGv_Disabled, |
| 69 | SaGv_FixedPoint0, |
| 70 | SaGv_FixedPoint1, |
| 71 | SaGv_FixedPoint2, |
| 72 | SaGv_FixedPoint3, |
| 73 | SaGv_Enabled, |
| 74 | } SaGv; |
| 75 | |
| 76 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 77 | uint8_t RMT; |
| 78 | |
| 79 | /* USB related */ |
| 80 | struct usb2_port_config usb2_ports[16]; |
| 81 | struct usb3_port_config usb3_ports[10]; |
| 82 | /* Wake Enable Bitmap for USB2 ports */ |
| 83 | uint16_t usb2_wake_enable_bitmap; |
| 84 | /* Wake Enable Bitmap for USB3 ports */ |
| 85 | uint16_t usb3_wake_enable_bitmap; |
| 86 | |
| 87 | /* SATA related */ |
| 88 | uint8_t SataEnable; |
| 89 | uint8_t SataMode; |
| 90 | uint8_t SataSalpSupport; |
| 91 | uint8_t SataPortsEnable[8]; |
| 92 | uint8_t SataPortsDevSlp[8]; |
| 93 | |
| 94 | /* |
| 95 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 96 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 97 | */ |
| 98 | uint8_t SataPwrOptimizeDisable; |
| 99 | |
| 100 | /* |
| 101 | * SATA Port Enable Dito Config. |
| 102 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 103 | */ |
| 104 | uint8_t SataPortsEnableDitoConfig[8]; |
| 105 | |
| 106 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 107 | uint8_t SataPortsDmVal[8]; |
| 108 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 109 | uint16_t SataPortsDitoVal[8]; |
| 110 | |
| 111 | /* Audio related */ |
| 112 | uint8_t PchHdaDspEnable; |
| 113 | uint8_t PchHdaAudioLinkHdaEnable; |
| 114 | uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; |
| 115 | uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; |
| 116 | uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; |
| 117 | uint8_t PchHdaIDispLinkTmode; |
| 118 | uint8_t PchHdaIDispLinkFrequency; |
| 119 | uint8_t PchHdaIDispCodecDisconnect; |
| 120 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame^] | 121 | struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; |
| 122 | struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; |
| 123 | uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 124 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 125 | /* Gfx related */ |
| 126 | enum { |
| 127 | IGD_SM_0MB = 0x00, |
| 128 | IGD_SM_32MB = 0x01, |
| 129 | IGD_SM_64MB = 0x02, |
| 130 | IGD_SM_96MB = 0x03, |
| 131 | IGD_SM_128MB = 0x04, |
| 132 | IGD_SM_160MB = 0x05, |
| 133 | IGD_SM_4MB = 0xF0, |
| 134 | IGD_SM_8MB = 0xF1, |
| 135 | IGD_SM_12MB = 0xF2, |
| 136 | IGD_SM_16MB = 0xF3, |
| 137 | IGD_SM_20MB = 0xF4, |
| 138 | IGD_SM_24MB = 0xF5, |
| 139 | IGD_SM_28MB = 0xF6, |
| 140 | IGD_SM_36MB = 0xF8, |
| 141 | IGD_SM_40MB = 0xF9, |
| 142 | IGD_SM_44MB = 0xFA, |
| 143 | IGD_SM_48MB = 0xFB, |
| 144 | IGD_SM_52MB = 0xFC, |
| 145 | IGD_SM_56MB = 0xFD, |
| 146 | IGD_SM_60MB = 0xFE, |
| 147 | } IgdDvmt50PreAlloc; |
| 148 | uint8_t InternalGfx; |
| 149 | uint8_t SkipExtGfxScan; |
| 150 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 151 | /* HeciEnabled decides the state of Heci1 at end of boot |
| 152 | * Setting to 0 (default) disables Heci1 and hides the device from OS */ |
| 153 | uint8_t HeciEnabled; |
| 154 | /* PL2 Override value in Watts */ |
| 155 | uint32_t tdp_pl2_override; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 156 | |
| 157 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 158 | uint8_t eist_enable; |
| 159 | |
| 160 | /* Enable C6 DRAM */ |
| 161 | uint8_t enable_c6dram; |
| 162 | /* |
| 163 | * PRMRR size setting with below options |
| 164 | * Disable: 0x0 |
| 165 | * 32MB: 0x2000000 |
| 166 | * 64MB: 0x4000000 |
| 167 | * 128 MB: 0x8000000 |
| 168 | * 256 MB: 0x10000000 |
| 169 | * 512 MB: 0x20000000 |
| 170 | */ |
| 171 | uint32_t PrmrrSize; |
| 172 | uint8_t PmTimerDisabled; |
| 173 | /* |
| 174 | * SerialIO device mode selection: |
| 175 | * PchSerialIoDisabled, |
| 176 | * PchSerialIoPci, |
| 177 | * PchSerialIoHidden, |
| 178 | * PchSerialIoLegacyUart, |
| 179 | * PchSerialIoSkipInit |
| 180 | */ |
| 181 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 182 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 183 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 184 | /* |
| 185 | * GSPIn Default Chip Select Mode: |
| 186 | * 0:Hardware Mode, |
| 187 | * 1:Software Mode |
| 188 | */ |
| 189 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 190 | /* |
| 191 | * GSPIn Default Chip Select State: |
| 192 | * 0: Low, |
| 193 | * 1: High |
| 194 | */ |
| 195 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 196 | |
| 197 | /* Debug interface selection */ |
| 198 | enum { |
| 199 | DEBUG_INTERFACE_RAM = (1 << 0), |
| 200 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
| 201 | DEBUG_INTERFACE_USB3 = (1 << 3), |
| 202 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
| 203 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 204 | } debug_interface_flag; |
| 205 | |
| 206 | /* Enable Pch iSCLK */ |
| 207 | uint8_t pch_isclk; |
| 208 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 209 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
| 210 | enum { |
| 211 | FORCE_DISABLE, |
| 212 | FORCE_ENABLE, |
| 213 | } CnviBtAudioOffload; |
| 214 | |
| 215 | /* |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 216 | * IOM Port Config |
| 217 | * If a port orientation needs to be controlled by the SOC this setting must be |
| 218 | * updated to reflect the correct GPIOs being used for the SOC port flipping. |
| 219 | * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down |
| 220 | * 0,1 are pull up and pull down for port 0 |
| 221 | * 2,3 are pull up and pull down for port 1 |
| 222 | * 4,5 are pull up and pull down for port 2 |
| 223 | * 6,7 are pull up and pull down for port 3 |
| 224 | * values to be programmed correspond to the GPIO family and offsets |
| 225 | */ |
| 226 | uint32_t IomTypeCPortPadCfg[8]; |
| 227 | |
| 228 | /* |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 229 | * SOC Aux orientation override: |
| 230 | * This is a bitfield that corresponds to up to 4 TCSS ports on ADL. |
| 231 | * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC. |
| 232 | * Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines |
| 233 | * on the motherboard. |
| 234 | */ |
| 235 | uint16_t TcssAuxOri; |
| 236 | |
| 237 | /* Connect Topology Command timeout value */ |
| 238 | uint16_t ITbtConnectTopologyTimeoutInMs; |
| 239 | |
| 240 | /* |
| 241 | * Override GPIO PM configuration: |
| 242 | * 0: Use FSP default GPIO PM program, |
| 243 | * 1: coreboot to override GPIO PM program |
| 244 | */ |
| 245 | uint8_t gpio_override_pm; |
| 246 | |
| 247 | /* |
| 248 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 249 | * Bit 6-7: Reserved |
| 250 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 251 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 252 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 253 | * Bit 2: MISCCFG_GSXLCGEN |
| 254 | * Bit 1: MISCCFG_GPDPCGEN |
| 255 | * Bit 0: MISCCFG_GPDLCGEN |
| 256 | */ |
| 257 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 258 | |
| 259 | /* DP config */ |
| 260 | /* |
| 261 | * Port config |
| 262 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 263 | */ |
| 264 | uint8_t DdiPortAConfig; |
| 265 | uint8_t DdiPortBConfig; |
| 266 | |
| 267 | /* Enable(1)/Disable(0) HPD */ |
| 268 | uint8_t DdiPortAHpd; |
| 269 | uint8_t DdiPortBHpd; |
| 270 | uint8_t DdiPortCHpd; |
| 271 | uint8_t DdiPort1Hpd; |
| 272 | uint8_t DdiPort2Hpd; |
| 273 | uint8_t DdiPort3Hpd; |
| 274 | uint8_t DdiPort4Hpd; |
| 275 | |
| 276 | /* Enable(1)/Disable(0) DDC */ |
| 277 | uint8_t DdiPortADdc; |
| 278 | uint8_t DdiPortBDdc; |
| 279 | uint8_t DdiPortCDdc; |
| 280 | uint8_t DdiPort1Ddc; |
| 281 | uint8_t DdiPort2Ddc; |
| 282 | uint8_t DdiPort3Ddc; |
| 283 | uint8_t DdiPort4Ddc; |
| 284 | |
| 285 | /* Hybrid storage mode enable (1) / disable (0) |
| 286 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 287 | * accordingly */ |
| 288 | uint8_t HybridStorageMode; |
| 289 | |
| 290 | /* |
| 291 | * Override CPU flex ratio value: |
| 292 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 293 | * Valid Range 0 to 63. |
| 294 | * |
| 295 | * In general descriptor provides option to set default cpu flex ratio. |
| 296 | * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. |
| 297 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 298 | * |
| 299 | * Only override CPU flex ratio if don't want to boot with non-turbo max. |
| 300 | */ |
| 301 | uint8_t cpu_ratio_override; |
| 302 | |
| 303 | /* |
| 304 | * Enable(0)/Disable(1) DMI Power Optimizer on PCH side. |
| 305 | * Default 0. Setting this to 1 disables the DMI Power Optimizer. |
| 306 | */ |
| 307 | uint8_t DmiPwrOptimizeDisable; |
| 308 | |
| 309 | /* |
| 310 | * Enable(1)/Disable(0) CPU Replacement check. |
| 311 | * Default 0. Setting this to 1 to check CPU replacement. |
| 312 | */ |
| 313 | uint8_t CpuReplacementCheck; |
| 314 | |
| 315 | /* ISA Serial Base selection. */ |
| 316 | enum { |
| 317 | ISA_SERIAL_BASE_ADDR_3F8, |
| 318 | ISA_SERIAL_BASE_ADDR_2F8, |
| 319 | } IsaSerialUartBase; |
| 320 | }; |
| 321 | |
| 322 | typedef struct soc_intel_alderlake_config config_t; |
| 323 | |
| 324 | #endif |