Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | a4b11e5c | 2017-02-03 18:57:49 +0530 | [diff] [blame] | 4 | * Copyright (C) 2016-2017 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 16 | #include <chip.h> |
Duncan Laurie | 7d48410 | 2017-01-09 22:23:39 -0800 | [diff] [blame] | 17 | #include <bootmode.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 18 | #include <bootstate.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <fsp/api.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 21 | #include <arch/acpi.h> |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 22 | #include <arch/io.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 23 | #include <chip.h> |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 24 | #include <compiler.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 25 | #include <bootstate.h> |
| 26 | #include <console/console.h> |
| 27 | #include <device/device.h> |
| 28 | #include <device/pci.h> |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 29 | #include <device/pci_ids.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 30 | #include <fsp/api.h> |
| 31 | #include <fsp/util.h> |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 32 | #include <intelblocks/xdci.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 33 | #include <romstage_handoff.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 34 | #include <soc/acpi.h> |
Patrick Georgi | c6a0050 | 2017-10-05 18:19:29 +0200 | [diff] [blame] | 35 | #include <soc/intel/common/vbt.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 36 | #include <soc/interrupt.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 37 | #include <soc/iomap.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 38 | #include <soc/irq.h> |
| 39 | #include <soc/pci_devs.h> |
| 40 | #include <soc/ramstage.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 41 | #include <soc/systemagent.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 42 | #include <string.h> |
| 43 | |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 44 | struct pcie_entry { |
| 45 | unsigned int devfn; |
| 46 | unsigned int func_count; |
| 47 | }; |
| 48 | |
| 49 | /* |
| 50 | * According to table 2-2 in doc#546717: |
| 51 | * PCI bus[function] ID |
| 52 | * D28:[F0 - F7] 0xA110 - 0xA117 |
| 53 | * D29:[F0 - F7] 0xA118 - 0xA11F |
| 54 | * D27:[F0 - F3] 0xA167 - 0xA16A |
| 55 | */ |
| 56 | static const struct pcie_entry pcie_table_skl_pch_h[] = { |
| 57 | {PCH_DEVFN_PCIE1, 8}, |
| 58 | {PCH_DEVFN_PCIE9, 8}, |
| 59 | {PCH_DEVFN_PCIE17, 4}, |
| 60 | }; |
| 61 | |
| 62 | /* |
| 63 | * According to table 2-2 in doc#564464: |
| 64 | * PCI bus[function] ID |
| 65 | * D28:[F0 - F7] 0xA290 - 0xA297 |
| 66 | * D29:[F0 - F7] 0xA298 - 0xA29F |
| 67 | * D27:[F0 - F7] 0xA2E7 - 0xA2EE |
| 68 | */ |
| 69 | static const struct pcie_entry pcie_table_kbl_pch_h[] = { |
| 70 | {PCH_DEVFN_PCIE1, 8}, |
| 71 | {PCH_DEVFN_PCIE9, 8}, |
| 72 | {PCH_DEVFN_PCIE17, 8}, |
| 73 | }; |
| 74 | |
| 75 | /* |
| 76 | * According to table 2-2 in doc#567995/545659: |
| 77 | * PCI bus[function] ID |
| 78 | * D28:[F0 - F7] 0x9D10 - 0x9D17 |
| 79 | * D29:[F0 - F3] 0x9D18 - 0x9D1B |
| 80 | */ |
| 81 | static const struct pcie_entry pcie_table_skl_pch_lp[] = { |
| 82 | {PCH_DEVFN_PCIE1, 8}, |
| 83 | {PCH_DEVFN_PCIE9, 4}, |
| 84 | }; |
| 85 | |
| 86 | /* |
| 87 | * If the PCIe root port at function 0 is disabled, |
| 88 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 89 | * The below function will swap the devfn of the first enabled device |
| 90 | * in devicetree and function 0 resides a pci device |
| 91 | * so that it won't confuse coreboot. |
| 92 | */ |
| 93 | static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group, |
| 94 | size_t pci_groups) |
| 95 | { |
| 96 | struct device *func0; |
| 97 | unsigned int devfn, devfn0; |
| 98 | int i, group; |
| 99 | unsigned int inc = PCI_DEVFN(0, 1); |
| 100 | |
| 101 | for (group = 0; group < pci_groups; group++) { |
| 102 | devfn0 = pcie_rp_group[group].devfn; |
| 103 | func0 = dev_find_slot(0, devfn0); |
| 104 | if (func0 == NULL) |
| 105 | continue; |
| 106 | |
| 107 | /* No more functions if function 0 is disabled. */ |
| 108 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 109 | continue; |
| 110 | |
| 111 | devfn = devfn0 + inc; |
| 112 | |
| 113 | /* |
| 114 | * Increase function by 1. |
| 115 | * Then find first enabled device to replace func0 |
| 116 | * as that port was move to func0. |
| 117 | */ |
| 118 | for (i = 1; i < pcie_rp_group[group].func_count; |
| 119 | i++, devfn += inc) { |
| 120 | struct device *dev = dev_find_slot(0, devfn); |
| 121 | if (dev == NULL || !dev->enabled) |
| 122 | continue; |
| 123 | |
| 124 | /* |
| 125 | * Found the first enabled device in |
| 126 | * a given dev number. |
| 127 | */ |
| 128 | printk(BIOS_INFO, "PCI func %d was swapped" |
| 129 | " to func 0.\n", i); |
| 130 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 131 | dev->path.pci.devfn = devfn0; |
| 132 | break; |
| 133 | } |
| 134 | } |
| 135 | } |
| 136 | |
| 137 | static void pcie_override_devicetree_after_silicon_init(void) |
| 138 | { |
| 139 | uint16_t id, id_mask; |
| 140 | |
| 141 | id = pci_read_config16(PCH_DEV_PCIE1, PCI_DEVICE_ID); |
| 142 | /* |
| 143 | * We may read an ID other than func 0 after FSP-S. |
| 144 | * Strip out 4 least significant bits. |
| 145 | */ |
| 146 | id_mask = id & ~0xf; |
| 147 | printk(BIOS_INFO, "Override DT after FSP-S, PCH is "); |
| 148 | if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 & ~0xf)) { |
| 149 | printk(BIOS_INFO, "KBL/SKL PCH-LP SKU\n"); |
| 150 | pcie_update_device_tree(&pcie_table_skl_pch_lp[0], |
| 151 | ARRAY_SIZE(pcie_table_skl_pch_lp)); |
| 152 | } else if (id_mask == (PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 & ~0xf)) { |
| 153 | printk(BIOS_INFO, "KBL PCH-H SKU\n"); |
| 154 | pcie_update_device_tree(&pcie_table_kbl_pch_h[0], |
| 155 | ARRAY_SIZE(pcie_table_kbl_pch_h)); |
| 156 | } else if (id_mask == (PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 & ~0xf)) { |
| 157 | printk(BIOS_INFO, "SKL PCH-H SKU\n"); |
| 158 | pcie_update_device_tree(&pcie_table_skl_pch_h[0], |
| 159 | ARRAY_SIZE(pcie_table_skl_pch_h)); |
| 160 | } else { |
| 161 | printk(BIOS_ERR, "[BUG] PCIE Root Port id 0x%x" |
| 162 | " is not found\n", id); |
| 163 | return; |
| 164 | } |
| 165 | } |
| 166 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 167 | void soc_init_pre_device(void *chip_info) |
| 168 | { |
| 169 | /* Perform silicon specific init. */ |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 170 | fsp_silicon_init(romstage_handoff_is_resume()); |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 171 | /* swap enabled PCI ports in device tree if needed */ |
| 172 | pcie_override_devicetree_after_silicon_init(); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 173 | } |
| 174 | |
Furquan Shaikh | c248044 | 2017-02-20 13:41:56 -0800 | [diff] [blame] | 175 | void soc_fsp_load(void) |
| 176 | { |
| 177 | fsps_load(romstage_handoff_is_resume()); |
| 178 | } |
| 179 | |
Elyes HAOUAS | 143fb46 | 2018-05-25 12:56:45 +0200 | [diff] [blame] | 180 | static void pci_domain_set_resources(struct device *dev) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 181 | { |
| 182 | assign_resources(dev->link_list); |
| 183 | } |
| 184 | |
| 185 | static struct device_operations pci_domain_ops = { |
| 186 | .read_resources = &pci_domain_read_resources, |
| 187 | .set_resources = &pci_domain_set_resources, |
| 188 | .scan_bus = &pci_domain_scan_bus, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 189 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Nico Huber | c37b0e3 | 2017-09-18 20:03:46 +0200 | [diff] [blame] | 190 | .write_acpi_tables = &northbridge_write_acpi_tables, |
| 191 | .acpi_name = &soc_acpi_name, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 192 | #endif |
| 193 | }; |
| 194 | |
| 195 | static struct device_operations cpu_bus_ops = { |
| 196 | .read_resources = DEVICE_NOOP, |
| 197 | .set_resources = DEVICE_NOOP, |
| 198 | .enable_resources = DEVICE_NOOP, |
Subrata Banik | a4b11e5c | 2017-02-03 18:57:49 +0530 | [diff] [blame] | 199 | .init = DEVICE_NOOP, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 200 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
| 201 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
| 202 | #endif |
| 203 | }; |
| 204 | |
Elyes HAOUAS | 143fb46 | 2018-05-25 12:56:45 +0200 | [diff] [blame] | 205 | static void soc_enable(struct device *dev) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 206 | { |
| 207 | /* Set the operations if it is a special bus type */ |
Subrata Banik | 3c838c7 | 2017-12-06 18:14:01 +0530 | [diff] [blame] | 208 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 209 | dev->ops = &pci_domain_ops; |
Subrata Banik | 3c838c7 | 2017-12-06 18:14:01 +0530 | [diff] [blame] | 210 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 211 | dev->ops = &cpu_bus_ops; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | struct chip_operations soc_intel_skylake_ops = { |
| 215 | CHIP_NAME("Intel 6th Gen") |
| 216 | .enable_dev = &soc_enable, |
| 217 | .init = &soc_init_pre_device, |
| 218 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 219 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 220 | /* UPD parameters to be initialized before SiliconInit */ |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 221 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 222 | { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 223 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 224 | FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; |
| 225 | static struct soc_intel_skylake_config *config; |
Patrick Georgi | d2990ff | 2018-05-03 18:06:15 +0200 | [diff] [blame] | 226 | uintptr_t vbt_data = (uintptr_t)vbt_get(); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 227 | int i; |
| 228 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 229 | struct device *dev = SA_DEV_ROOT; |
| 230 | if (!dev || !dev->chip_info) { |
| 231 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 232 | return; |
| 233 | } |
| 234 | config = dev->chip_info; |
| 235 | |
| 236 | mainboard_silicon_init_params(params); |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 237 | /* Set PsysPmax if it is available from DT */ |
| 238 | if (config->psys_pmax) { |
| 239 | /* PsysPmax is in unit of 1/8 Watt */ |
| 240 | tconfig->PsysPmax = config->psys_pmax * 8; |
| 241 | printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); |
| 242 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 243 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 244 | params->GraphicsConfigPtr = (u32) vbt_data; |
| 245 | |
| 246 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 247 | params->PortUsb20Enable[i] = |
| 248 | config->usb2_ports[i].enable; |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 249 | params->Usb2OverCurrentPin[i] = |
| 250 | config->usb2_ports[i].ocpin; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 251 | params->Usb2AfePetxiset[i] = |
| 252 | config->usb2_ports[i].pre_emp_bias; |
| 253 | params->Usb2AfeTxiset[i] = |
| 254 | config->usb2_ports[i].tx_bias; |
| 255 | params->Usb2AfePredeemp[i] = |
| 256 | config->usb2_ports[i].tx_emp_enable; |
| 257 | params->Usb2AfePehalfbit[i] = |
| 258 | config->usb2_ports[i].pre_emp_bit; |
| 259 | } |
| 260 | |
| 261 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 262 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2c3054c | 2016-11-22 20:21:49 +0530 | [diff] [blame] | 263 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 264 | if (config->usb3_ports[i].tx_de_emp) { |
| 265 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 266 | params->Usb3HsioTxDeEmph[i] = |
| 267 | config->usb3_ports[i].tx_de_emp; |
| 268 | } |
| 269 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 270 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 271 | params->Usb3HsioTxDownscaleAmp[i] = |
| 272 | config->usb3_ports[i].tx_downscale_amp; |
| 273 | } |
| 274 | } |
| 275 | |
| 276 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 277 | sizeof(params->SataPortsEnable)); |
| 278 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 279 | sizeof(params->SataPortsDevSlp)); |
| 280 | memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, |
| 281 | sizeof(params->PcieRpClkReqSupport)); |
| 282 | memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, |
| 283 | sizeof(params->PcieRpClkReqNumber)); |
Rizwan Qureshi | 6ab4ed4 | 2017-09-05 14:18:25 +0530 | [diff] [blame] | 284 | memcpy(params->PcieRpAdvancedErrorReporting, |
| 285 | config->PcieRpAdvancedErrorReporting, |
| 286 | sizeof(params->PcieRpAdvancedErrorReporting)); |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 287 | memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, |
| 288 | sizeof(params->PcieRpLtrEnable)); |
Duncan Laurie | 74ea48e | 2018-01-29 12:00:47 -0800 | [diff] [blame] | 289 | memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, |
| 290 | sizeof(params->PcieRpHotPlug)); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 291 | |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 292 | /* |
| 293 | * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for |
| 294 | * all the enabled PCIe root ports, invalid(0x1F) is set for |
| 295 | * disabled PCIe root ports. |
| 296 | */ |
| 297 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 298 | if (config->PcieRpClkReqSupport[i]) |
| 299 | params->PcieRpClkSrcNumber[i] = |
| 300 | config->PcieRpClkSrcNumber[i]; |
| 301 | else |
| 302 | params->PcieRpClkSrcNumber[i] = 0x1F; |
| 303 | } |
| 304 | |
Naresh G Solanki | eedf6d8 | 2016-11-16 21:27:38 +0530 | [diff] [blame] | 305 | /* disable Legacy PME */ |
| 306 | memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |
| 307 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 308 | memcpy(params->SerialIoDevMode, config->SerialIoDevMode, |
| 309 | sizeof(params->SerialIoDevMode)); |
| 310 | |
| 311 | params->PchCio2Enable = config->Cio2Enable; |
Rizwan Qureshi | c2c8a74 | 2017-01-13 22:04:11 +0530 | [diff] [blame] | 312 | params->SaImguEnable = config->SaImguEnable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 313 | params->Heci3Enabled = config->Heci3Enabled; |
| 314 | |
| 315 | params->LogoPtr = config->LogoPtr; |
| 316 | params->LogoSize = config->LogoSize; |
| 317 | |
| 318 | params->CpuConfig.Bits.VmxEnable = config->VmxEnable; |
| 319 | |
| 320 | params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; |
| 321 | params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; |
| 322 | params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 323 | |
| 324 | params->PchLanEnable = config->EnableLan; |
Duncan Laurie | 14485ef | 2017-12-13 13:58:35 -0800 | [diff] [blame] | 325 | if (config->EnableLan) { |
| 326 | params->PchLanLtrEnable = config->EnableLanLtr; |
| 327 | params->PchLanK1OffEnable = config->EnableLanK1Off; |
| 328 | params->PchLanClkReqSupported = config->LanClkReqSupported; |
| 329 | params->PchLanClkReqNumber = config->LanClkReqNumber; |
| 330 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 331 | params->SataSalpSupport = config->SataSalpSupport; |
| 332 | params->SsicPortEnable = config->SsicPortEnable; |
| 333 | params->ScsEmmcEnabled = config->ScsEmmcEnabled; |
| 334 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 335 | params->ScsSdCardEnabled = config->ScsSdCardEnabled; |
| 336 | params->PchIshEnable = config->IshEnable; |
| 337 | params->PchHdaEnable = config->EnableAzalia; |
| 338 | params->PchHdaIoBufferOwnership = config->IoBufferOwnership; |
| 339 | params->PchHdaDspEnable = config->DspEnable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 340 | params->Device4Enable = config->Device4Enable; |
| 341 | params->SataEnable = config->EnableSata; |
| 342 | params->SataMode = config->SataMode; |
Matt DeVillier | 9e0d69b | 2017-10-10 14:03:36 -0500 | [diff] [blame] | 343 | params->SataSpeedLimit = config->SataSpeedLimit; |
Kane Chen | 14e0fa5 | 2017-12-27 12:11:23 +0800 | [diff] [blame] | 344 | params->SataPwrOptEnable = config->SataPwrOptEnable; |
Matt DeVillier | 9e0d69b | 2017-10-10 14:03:36 -0500 | [diff] [blame] | 345 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 346 | tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 347 | tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 348 | /* |
| 349 | * To disable HECI, the Psf needs to be left unlocked |
| 350 | * by FSP till end of post sequence. Based on the devicetree |
| 351 | * setting, we set the appropriate PsfUnlock policy in FSP, |
| 352 | * do the changes and then lock it back in coreboot during finalize. |
| 353 | */ |
| 354 | tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; |
Subrata Banik | c204aaa | 2017-08-17 15:49:58 +0530 | [diff] [blame] | 355 | if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { |
| 356 | tconfig->PchLockDownBiosInterface = 0; |
| 357 | params->PchLockDownBiosLock = 0; |
| 358 | params->PchLockDownSpiEiss = 0; |
| 359 | /* |
| 360 | * Skip Spi Flash Lockdown from inside FSP. |
| 361 | * Making this config "0" means FSP won't set the FLOCKDN bit |
| 362 | * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). |
| 363 | * So, it becomes coreboot's responsibility to set this bit |
| 364 | * before end of POST for security concerns. |
| 365 | */ |
| 366 | params->SpiFlashCfgLockDown = 0; |
| 367 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 368 | params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; |
| 369 | params->PchSubSystemId = config->PchConfigSubSystemId; |
| 370 | params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; |
| 371 | params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 372 | params->PchPmDeepSxPol = config->PmConfigDeepSxPol; |
Duncan Laurie | 25c7d93 | 2017-02-17 17:16:43 -0800 | [diff] [blame] | 373 | params->PchPmSlpS0Enable = config->s0ix_enable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 374 | params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; |
| 375 | params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; |
| 376 | params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; |
| 377 | params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; |
| 378 | params->PchPmLpcClockRun = config->PmConfigPciClockRun; |
| 379 | params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; |
| 380 | params->PchPmPwrBtnOverridePeriod = |
| 381 | config->PmConfigPwrBtnOverridePeriod; |
| 382 | params->PchPmPwrCycDur = config->PmConfigPwrCycDur; |
Rizwan Qureshi | 0da186c | 2017-02-23 14:43:39 +0530 | [diff] [blame] | 383 | |
| 384 | /* Indicate whether platform supports Voltage Margining */ |
| 385 | params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; |
| 386 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 387 | params->PchSirqEnable = config->SerialIrqConfigSirqEnable; |
| 388 | params->PchSirqMode = config->SerialIrqConfigSirqMode; |
| 389 | |
Subrata Banik | ce23d4c | 2018-06-04 10:05:07 +0530 | [diff] [blame] | 390 | params->CpuConfig.Bits.SkipMpInit = !config->use_fsp_mp_init; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 391 | |
| 392 | for (i = 0; i < ARRAY_SIZE(config->i2c); i++) |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 393 | params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 394 | |
| 395 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 396 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
| 397 | |
| 398 | /* Show SPI controller if enabled in devicetree.cb */ |
| 399 | dev = dev_find_slot(0, PCH_DEVFN_SPI); |
| 400 | params->ShowSpiController = dev->enabled; |
| 401 | |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 402 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 403 | dev = dev_find_slot(0, PCH_DEVFN_USBOTG); |
| 404 | if (!xdci_can_enable()) |
| 405 | dev->enabled = 0; |
| 406 | params->XdciEnable = dev->enabled; |
| 407 | |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 408 | /* |
| 409 | * Send VR specific mailbox commands: |
| 410 | * 000b - no VR specific command sent |
| 411 | * 001b - VR mailbox command specifically for the MPS IMPV8 VR |
Lee Leahy | f4c4ab9 | 2017-03-16 17:08:03 -0700 | [diff] [blame] | 412 | * will be sent |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 413 | * 010b - VR specific command sent for PS4 exit issue |
| 414 | * 100b - VR specific command sent for MPS VR decay issue |
| 415 | */ |
| 416 | params->SendVrMbxCmd1 = config->SendVrMbxCmd; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 417 | |
Rizwan Qureshi | b3e18c7 | 2017-09-25 17:35:15 +0530 | [diff] [blame] | 418 | /* |
| 419 | * Activates VR mailbox command for Intersil VR C-state issues. |
| 420 | * 0 - no mailbox command sent. |
| 421 | * 1 - VR mailbox command sent for IA/GT rails only. |
| 422 | * 2 - VR mailbox command sent for IA/GT/SA rails. |
| 423 | */ |
| 424 | params->IslVrCmd = config->IslVrCmd; |
| 425 | |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 426 | /* Acoustic Noise Mitigation */ |
| 427 | params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
| 428 | params->SlowSlewRateForIa = config->SlowSlewRateForIa; |
| 429 | params->SlowSlewRateForGt = config->SlowSlewRateForGt; |
| 430 | params->SlowSlewRateForSa = config->SlowSlewRateForSa; |
| 431 | params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa; |
| 432 | params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; |
| 433 | params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; |
| 434 | |
Rizwan Qureshi | ffe5810 | 2017-02-10 15:58:24 +0530 | [diff] [blame] | 435 | /* Enable PMC XRAM read */ |
| 436 | tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; |
| 437 | |
Subrata Banik | 6b45ee4 | 2017-05-12 11:43:57 +0530 | [diff] [blame] | 438 | /* Enable/Disable EIST */ |
| 439 | tconfig->Eist = config->eist_enable; |
| 440 | |
marxwang | ec5a947 | 2017-12-11 14:57:49 +0800 | [diff] [blame] | 441 | /* Set TccActivationOffset */ |
| 442 | tconfig->TccActivationOffset = config->tcc_offset; |
| 443 | |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 444 | /* Enable VT-d and X2APIC */ |
| 445 | if (!config->ignore_vtd && soc_is_vtd_capable()) { |
| 446 | params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; |
| 447 | params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; |
| 448 | params->X2ApicOptOut = 0; |
| 449 | tconfig->VtdDisable = 0; |
| 450 | |
| 451 | params->PchIoApicBdfValid = 1; |
| 452 | params->PchIoApicBusNumber = 250; |
| 453 | params->PchIoApicDeviceNumber = 31; |
| 454 | params->PchIoApicFunctionNumber = 0; |
| 455 | } |
| 456 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 457 | soc_irq_settings(params); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 458 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 459 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 460 | /* Mainboard GPIO Configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 461 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 462 | { |
| 463 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 464 | } |