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review.coreboot.org / coreboot / bf08da27d56f12e9176fc419f39b4951cd46a8f2 / . / Documentation / Intel / Board / board.html
blob: e15778096240143d4148bb74b13c23a3512430d8 [file] [log] [blame]
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>Board</title>
5 </head>
6 <body>
7
8<h1>x86 Board Development</h1>
9<p>
10 Board development requires System-on-a-Chip (SoC) support.
11 The combined steps are listed
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]12 <a target="_blank" href="../development.html">here</a>.
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]13 The development steps for the board are listed below:
14</p>
15<ol>
16 <li><a href="#RequiredFiles">Required Files</a></li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]17 <li>Enable <a href="#SerialOutput">Serial Output</a></li>
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]18 <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]19 <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame^]20 <li><a href="#AcpiTables">ACPI Tables</a></li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]21</ol>
22
23
24<hr>
25<h1><a name="RequiredFiles">Required Files</a></h1>
26<p>
27 Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
28</p>
29
30<p>
31 The following files are required to build a new board:
32</p>
33<ol>
34 <li>Kconfig.name - Defines the Kconfig value for the board</li>
35 <li>Kconfig
36 <ol type="A">
37 <li>Selects the SoC for the board and specifies the SPI flash size
38 <ol type="I">
39 <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
40 <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
41 </ol>
42 </li>
43 <li>Declare the Kconfig values for:
44 <ol type="I">
45 <li>MAINBOARD_DIR</li>
46 <li>MAINBOARD_PART_NUMBER</li>
47 <li>MAINBOARD_VENDOR</li>
48 </ol>
49 </li>
50 </ol>
51 </li>
52 <li>devicetree.cb - Enable root bridge and serial port
53 <ol type="A">
54 <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
55 this path is used by the generated static.c to include the chip.h
56 header file
57 </li>
58 </ol>
59 </li>
60 <li>romstage.c
61 <ol type="A">
62 <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
63 </ol>
64 </li>
65 <li>Configure coreboot build:
66 <ol type="A">
67 <li>Set LOCALVERSION</li>
68 <li>FLASHMAP_OFFSET = 0x00700000</li>
69 <li>Select vendor for the board</li>
70 <li>Select the board</li>
71 <li>CBFS_SIZE = 0x00100000</li>
72 <li>Set the CPU_MICROCODE_CBFS_LEN</li>
73 <li>Set the CPU_MICROCODE_CBFS_LOC</li>
74 <li>Set the FSP_IMAGE_ID_STRING</li>
75 <li>Set the FSP_LOC</li>
76 <li>Disable GOP_SUPPORT</li>
77 <li>No payload</li>
78 <li>Choose the default value for all other options</li>
79 </ol>
80 </li>
81</ol>
82
83
84<hr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]85<h1><a name="SerialOutput">Enable Serial Output</a></h1>
86<p>
87 Use the following steps to enable serial output:
88</p>
89<ol>
90 <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
91 file:
92 <ol type="A">
93 <li>Power on and enable the UART controller</li>
94 <li>Connect the UART receive and transmit data lines to the
95 appropriate SoC pins
96 </li>
97 </ol>
98 </li>
99 <li>Add Makefile.inc
100 <ol type="A">
101 <li>Add com_init.c to romstage</li>
102 </ol>
103 </li>
104</ol>
105
106
Lee Leahyfcf776f2016-02-04 11:23:36 -0800[diff] [blame]107<hr>
108<h1><a name="SpdData">Memory Timing Data</a></h1>
109<p>
110 Memory timing data is located in the flash. This data is in the format of
111 <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
112 (SPD) data.
113 Use the following steps to load the SPD data:
114</p>
115<ol>
116 <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
117 display of the SPD data being passed to MemoryInit
118 </li>
119 <li>Create an "spd" subdirectory</li>
120 <li>Create an spd/spd.c file for the SPD implementation
121 <ol type="A">
122 <li>Implement the mainboard_fill_spd_data routine
123 <ol type="i">
124 <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
125 <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
126 <li>Set the DIMM channel configuration</li>
127 </ol>
128 </li>
129 </ol>
130 </li>
131 <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
132 <li>Create spd/Makefile.inc
133 <ol type="A">
134 <li>Add spd.c to romstage</li>
135 <li>Add the .spd.hex file to SPD_SOURCES</li>
136 </ol>
137 </li>
138 <li>Edit Makefile.inc to add the spd subdirectory</li>
139 <li>Edit romstage.c
140 <ol type="A">
141 <li>Call mainboard_fill_spd_data</li>
142 <li>Add mainboard_memory_init_params to copy the SPD and DRAM
143 configuration data from the pei_data structure into the UPDs
144 for MemoryInit
145 </li>
146 </ol>
147 </li>
148 <li>Edit devicetree.cb
149 <ol type="A">
150 <li>Include the UPD parameters for MemoryInit except for:
151 <ul>
152 <li>Address of SPD data</li>
153 <li>DRAM configuration set above</li>
154 </ul>
155 </li>
156 </ol>
157 </li>
158 <li>A working FSP
159 <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
160 routine is required to complete debugging</li>
161 <li>Debug the result until port 0x80 outputs
162 <ol type="A">
163 <li>0x34:
164 - Just after entering
165 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
166 </li>
167 <li>0x36:
168 - Just before displaying the
169 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
170 for FSP MemoryInit
171 </li>
172 <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
173 - Just before calling FSP
174 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
175 </li>
176 <li>0x37:
177 - Just after returning from FSP
178 <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
179 </li>
180 </ol>
181 </li>
182 <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
183</ol>
184
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]185
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]186
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]187<hr>
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]188<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1>
189<p>
190 Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
191 of the devices in the system. Edit the devicetree.cb file:
192</p>
193<ol>
194 <li>Edit the devicetree.cb file:
195 <ol type="A">
196 <li>Add an entry for a PCI device.function and turn it off. The entry
197 should look similar to:
198<pre><code>device pci 14.0 off end</code></pre>
199 </li>
200 <li>Turn on the devices for:
201 <ul>
202 <li>Memory Controller</li>
203 <li>Debug serial device</li>
204 </ul>
205 </li>
206 </ol>
207 </li>
208 <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
209</ol>
210
211
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame^]212
Lee Leahyde8c7e32016-02-14 14:55:29 -0800[diff] [blame]213<hr>
Lee Leahybf08da22016-02-20 17:48:35 -0800[diff] [blame^]214<h1><a name="AcpiTables">ACPI Tables</a></h1>
215<ol>
216 <li>Edit Kconfig
217 <ol type="A">
218 <li>Add "select HAVE_ACPI_TABLES"</li>
219 </ol>
220 </li>
221 <li>Add the acpi_tables.c module:
222 <ol type="A">
223 <li>Include soc/acpi.h</li>
224 <li>Add the acpi_create_fadt routine
225 <ol type="I">
226 <li>fill in the ACPI header</li>
227 <li>Call the acpi_fill_in_fadt routine</li>
228 </ol>
229 </li>
230 </ol>
231 </li>
232 <li>Add the dsdt.asl module:
233 </li>
234</ol>
235
236
237
238<hr>
239<p>Modified: 20 February 2016</p>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]240 </body>
241</html>