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review.coreboot.org / coreboot / 66decf16446eeb8d3b2da93d0b0086a583bc17bf / . / Documentation / Intel / Board / board.html
blob: d50ff4e74f78b21702ee62ce36768ef56b813b02 [file] [log] [blame]
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>Board</title>
5 </head>
6 <body>
7
8<h1>x86 Board Development</h1>
9<p>
10 Board development requires System-on-a-Chip (SoC) support.
11 The combined steps are listed
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]12 <a target="_blank" href="../development.html">here</a>.
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]13 The development steps for the board are listed below:
14</p>
15<ol>
16 <li><a href="#RequiredFiles">Required Files</a></li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame^]17 <li>Enable <a href="#SerialOutput">Serial Output</a></li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]18</ol>
19
20
21<hr>
22<h1><a name="RequiredFiles">Required Files</a></h1>
23<p>
24 Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
25</p>
26
27<p>
28 The following files are required to build a new board:
29</p>
30<ol>
31 <li>Kconfig.name - Defines the Kconfig value for the board</li>
32 <li>Kconfig
33 <ol type="A">
34 <li>Selects the SoC for the board and specifies the SPI flash size
35 <ol type="I">
36 <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
37 <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
38 </ol>
39 </li>
40 <li>Declare the Kconfig values for:
41 <ol type="I">
42 <li>MAINBOARD_DIR</li>
43 <li>MAINBOARD_PART_NUMBER</li>
44 <li>MAINBOARD_VENDOR</li>
45 </ol>
46 </li>
47 </ol>
48 </li>
49 <li>devicetree.cb - Enable root bridge and serial port
50 <ol type="A">
51 <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
52 this path is used by the generated static.c to include the chip.h
53 header file
54 </li>
55 </ol>
56 </li>
57 <li>romstage.c
58 <ol type="A">
59 <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
60 </ol>
61 </li>
62 <li>Configure coreboot build:
63 <ol type="A">
64 <li>Set LOCALVERSION</li>
65 <li>FLASHMAP_OFFSET = 0x00700000</li>
66 <li>Select vendor for the board</li>
67 <li>Select the board</li>
68 <li>CBFS_SIZE = 0x00100000</li>
69 <li>Set the CPU_MICROCODE_CBFS_LEN</li>
70 <li>Set the CPU_MICROCODE_CBFS_LOC</li>
71 <li>Set the FSP_IMAGE_ID_STRING</li>
72 <li>Set the FSP_LOC</li>
73 <li>Disable GOP_SUPPORT</li>
74 <li>No payload</li>
75 <li>Choose the default value for all other options</li>
76 </ol>
77 </li>
78</ol>
79
80
81<hr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame^]82<h1><a name="SerialOutput">Enable Serial Output</a></h1>
83<p>
84 Use the following steps to enable serial output:
85</p>
86<ol>
87 <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
88 file:
89 <ol type="A">
90 <li>Power on and enable the UART controller</li>
91 <li>Connect the UART receive and transmit data lines to the
92 appropriate SoC pins
93 </li>
94 </ol>
95 </li>
96 <li>Add Makefile.inc
97 <ol type="A">
98 <li>Add com_init.c to romstage</li>
99 </ol>
100 </li>
101</ol>
102
103
104
105<hr>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]106<p>Modified: 31 January 2016</p>
107 </body>
108</html>